IS43R16800A-6T ISSI [Integrated Silicon Solution, Inc], IS43R16800A-6T Datasheet - Page 27

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IS43R16800A-6T

Manufacturer Part Number
IS43R16800A-6T
Description
8Meg x 16 128-MBIT DDR SDRAM
Manufacturer
ISSI [Integrated Silicon Solution, Inc]
Datasheet
IS43R16800A-6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
Command Intervals
A Read command to the consecutive Read command Interval
1. Same
2. Same
3. Different
Destination row of the
consecutive read command
Bank
address
Command
Address
DQS
/CK
DQ
CK
BA
Row address State
Same
Different
Any
READ to READ Command Interval (same ROW address in the same bank)
Bank0
Active
ACT
Row
t0
ACTIVE
ACTIVE
IDLE
NOP
Column = A
Read
Column A
READ
t3
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
Column B
Column = B
Read
READ
t4
t5
Column = A
Dout
out
A0
out
A1
t6
out
B0
Column = B
Dout
out
B1
NOP
t7
out
B2
out
B3
t8
t9
CL = 2
BL = 4
Bank0
ISSI
27
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