M95010-W STMICROELECTRONICS [STMicroelectronics], M95010-W Datasheet
M95010-W
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M95010-W Summary of contents
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... Table 1. Device summary Reference M95040 M95040 M95040-W M95040-R M95020 M95020 M95020-W M95020-R M95010 M95010 M95010-W M95010-R March 2008 Part number Rev 8 M95040 M95020 M95010 with high-speed clock SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width UFDFPN8 (MB) 2 × 1/42 www ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ...
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... UFDFPN8 (MLP8) — 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 25. Available M95010 products (package, voltage range, temperature grade Table 26. Available M95020 products (package, voltage range, temperature grade Table 27. Available M95040 products (package, voltage range, temperature grade Table 28 ...
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... M95040, M95020, M95010 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 ...
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... The M95040 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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... M95040, M95020, M95010 Table 2. Signal names Signal name HOLD Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Description 7/42 ...
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... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/42 must be held stable and within the specified valid range: CC Table 13 to Table 16). These signals are described next. M95040, M95020, M95010 , ...
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... M95040, M95020, M95010 2.6 Write Protect (W) This input signal is used to control whether the memory is write protected. When Write Protect (W) is held low, writes to the memory are disabled, but other operations remain enabled. Write Protect (W) must either be driven high or low, but must not be left floating. ...
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... At power-down (continuous decrease in V the device must be: ● deselected (Chip Select S should be allowed to follow the voltage applied on V ● in Standby Power mode (that should not be any internal write cycle in progress) 10/42 M95040, M95020, M95010 reaches the minimum CC below the minimum VCC operating voltage ...
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... M95040, M95020, M95010 3 Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low ...
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... Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 4. SPI modes supported CPOL CPHA 12/42 MSB M95040, M95020, M95010 Figure 4, is the clock polarity when the MSB AI01438B ...
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... M95040, M95020, M95010 4 Operating features 4.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. ...
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... Protected array addresses Protected block M95040 none none Upper quarter 180h - 1FFh Upper half 100h - 1FFh Whole memory 000h - 1FFh M95040, M95020, M95010 M95020 M95010 none none C0h - FFh 60h - 7Fh 80h - FFh 40h - 7Fh 00h - FFh 00h - 7Fh ...
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... M95040, M95020, M95010 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD W Control Logic Address Register and Counter Figure 6. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder Memory organization Status Register Size of the Read only EEPROM area ...
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... Read from Memory Array Write to Memory Array 7, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q M95040, M95020, M95010 Table 4. Table 4), the device automatically Instruction Format (1) 0000 X110 (1) 0000 X100 (1) 0000 X101 (1) 0000 X001 ...
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... M95040, M95020, M95010 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high ...
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... Hardware Protected mode has not been set. Table 5. Status Register format 18/ send this instruction to the device, Chip Select (S) is first driven low. Table 3) becomes protected against Write 1 1 M95040, M95020, M95010 BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit b0 WIP ...
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... M95040, M95020, M95010 Figure 9. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI01444D 19/42 ...
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... Chip Select (S) is first driven (as specified in Table Instruction 7 6 High Impedance MSB M95040, M95020, M95010 Table 20), at the end of which the Write Status Register AI01445B ...
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... M95040, M95020, M95010 6.5 Read from Memory Array (READ) As shown in Figure low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in register, and the byte of data at that address is shifted out, on Serial Data Output (Q) ...
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... Instruction Byte Address Table 6, the most significant address bits are Don’t Care. M95040, M95020, M95010 Table 13 to Table 20). After this Figure 13, the next byte Data Byte ...
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... M95040, M95020, M95010 Figure 13. Page Write (WRITE) sequence Depending on the memory size, as shown Instruction Byte Address ...
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... The BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1 and BP0) bits are initialized to 0. 24/42 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Input and output timing reference voltages 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 14. AC test measurement I/O waveform 26/42 Parameter Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC M95040, M95020, M95010 Min. Max. Unit 4.5 5.5 –40 125 °C Min. Max. Unit 2 ...
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... M95040, M95020, M95010 Table 12. Capacitance Symbol C Output Capacitance (Q) OUT C Input Capacitance (D) IN Input Capacitance (other pins) 1. Sampled only, not 100% tested Table 13. DC characteristics (M950x0, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current ...
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... –0 – –0 M95040, M95020, M95010 Min. Max. Unit ± 2 µA ± 2 µ µA –0. 0 Min. Max. ...
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... M95040, M95020, M95010 Table 17. AC characteristics (M950x0, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time M95040, M95020, M95010 and Table 9 Min. Max. Unit D.C. 10 MHz ...
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... M95040, M95020, M95010 Table 19. AC characteristics (M950x0-W, Device Grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time M95040, M95020, M95010 and Table 10 Min. Max. Unit D.C. 5 MHz ...
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... M95040, M95020, M95010 Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD tSLCH tCHDX tCLCH MSB IN High Impedance tHLCH tCLHL tHLQZ DC and AC parameters tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B 33/42 ...
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... DC and AC parameters Figure 17. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 34/42 tCH tCLQV tQLQH tQHQL M95040, M95020, M95010 tCL tSHQZ LSB OUT AI01449e ...
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... M95040, M95020, M95010 10 Package mechanical data In order to meet environmental requirements, ST offers the M95040 in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Typ Min Max 1.2 0.05 0.15 1 0.8 1.05 0.19 0.3 0.09 0.2 0.1 3 2.9 3.1 0. 6.4 6.2 6.6 4.4 4.3 4.5 0.6 0.45 0.75 1 0° 8° 8 M95040, M95020, M95010 TSSOP8AM (1) inches Typ Min Max 0.0472 0.002 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 0.1181 0.1142 0.122 0.0256 - - 0.252 0.2441 0.2598 0.1732 0.1693 0.1772 0.0236 0.0177 ...
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... M95040, M95020, M95010 Figure 20. UFDFPN8 (MLP8) — 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline 1. Drawing is not to scale. Table 23. UFDFPN8 (MLP8) — 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package mechanical data ...
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... The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for device grade 3 For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 38/42 (1) . ® (RoHS compliant) M95040, M95020, M95010 M95040 – ...
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... Table 26. Available M95020 products (package, voltage range, temperature grade) Package SO8N (MN) TSSOP8 (DW) MLP8 (MB) Table 27. Available M95040 products (package, voltage range, temperature grade) Package SO8N (MN) TSSOP8 (DW) MLP8 (MB) M95010-R M95010-W 1 5 5.5 V Range6 Range6 Range6 Range6 - - M95020-R M95020-W 1 5 5.5 V Range6 ...
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... Order information for Tape and Reel changed to T. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX 6.0 corrected to tHHQV. Signal Description updated. 10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified M95040, M95020, M95010 Changes , t substituted in AC CHHL CHHH (min) improved to -0.45V ...
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... M95040, M95020, M95010 Table 28. Document revision history (continued) Date Version 06-Nov-2006 20-Mar-2008 Document converted to new template, moved to below Section 6.3: Read Status Register PDIP package removed. UFDFPN8 (MB) package added (see and Table 23) and SO8N package specifications updated (see and Table 21). Packages are ECOPACK® compliant. ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 42/42 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M95040, M95020, M95010 ...