M95010-W STMICROELECTRONICS [STMicroelectronics], M95010-W Datasheet - Page 20

• Manufacturer Part Number: M95010-W
• Description: 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Instructions
6.4
20/42
Write Status Register (WRSR)
This instruction has no effect on bits b7, b6, b5, b4, b1 and b0 of the Status Register.
As shown in
low. The bits of the instruction byte and data byte are then shifted in on Serial Data Input
(D).
The instruction is terminated by driving Chip Select (S) high. Chip Select (S) must be driven
high after the rising edge of Serial Clock (C) that latches the eighth bit of the data byte, and
before the next rising edge of Serial Clock (C). If this condition is not met, the Write Status
Register (WRSR) instruction is not executed. The self-timed Write Cycle starts, and
continues for a period t
in Progress (WIP) bit is reset to 0.
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
Figure 10. Write Status Register (WRSR) sequence
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write Cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, after the
eighth bit, b0, of the data byte has been latched in
if Write Protect (W) is low.
S
C
D
Q
Figure
10, to send this instruction to the device, Chip Select (S) is first driven
0
W
(as specified in
1
High Impedance
2
Instruction
3
4
5
6
Table 13
7
MSB
7
8
6
9 10 11 12 13 14 15
to
5
Table
Register In
4
Status
3
20), at the end of which the Write
2
1
M95040, M95020, M95010
0
AI01445B