M95010-W STMICROELECTRONICS [STMicroelectronics], M95010-W Datasheet - Page 17

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M95010-W

Manufacturer Part Number
M95010-W
Description
4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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M95040, M95020, M95010
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Figure 8.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Protect (W) line being held low.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
8, to send this instruction to the device, Chip Select (S) is driven low,
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI03790D
Instructions
17/42

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