M95010-W STMICROELECTRONICS [STMicroelectronics], M95010-W Datasheet - Page 14

• Manufacturer Part Number: M95010-W
• Description: 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Operating features
4.3
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Data protection and protocol control
To help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows:
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●
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For any instruction to be accepted and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the "next rising edge of CLOCK" might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.
Table 3.
Status Register bits
BP1
The WEL bit is reset at power-up.
Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status Register).
Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected.
Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
0
0
1
1
Write-protected block size
BP0
0
1
0
1
Protected block
Whole memory
Upper quarter
Upper half
none
180h - 1FFh
100h - 1FFh
000h - 1FFh
M95040
none
Protected array addresses
C0h - FFh
80h - FFh
00h - FFh
M95020
none
M95040, M95020, M95010
60h - 7Fh
40h - 7Fh
00h - 7Fh
M95010
none