NAND02G-B2D NUMONYX [Numonyx B.V], NAND02G-B2D Datasheet - Page 27

• Manufacturer Part Number: NAND02G-B2D
• Description: 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

NAND02G-B2D
6.4
Multiplane page program
The devices support multiplane page program operations, which enables the programming
of two pages in parallel, one in each plane.
A multiplane page program operation requires the following two steps:
1.
2.
As for standard page program operation, the device supports random data input during both
data loading phases.
Once the multiplane page program operation has started, that is during a delay of t
Status register can be read using the Read Status register command.
Once the multiplane page program operation has completed, the P/E/R controller bit SR6 is
set to ‘1’ and the Ready/Busy signal goes High.
If the multiplane page program fails, an error is signaled on bit SR0 of the Status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see
Figure 12
related to the multiplane page program and the differences between ONFI 1.0 and
traditional sequences.
The first step serially loads up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
–
–
–
Parallel programming of both pages starts after the issue of Page Confirm command.
Refer to
and traditional sequences.
1 clock cycle to set up the Page Program command (see
input)
5 bus write cycles to input the first page address and data. The address of the first
page must be within the first plane (A18 = 0 for x 8 devices, A17 = 0 for x 16
devices)
1 bus write cycle to issue the page program confirm code. After this, the device is
busy for a time of t
When the device returns to the ready state (Ready/Busy High), a multiplane page
program setup code must be issued, followed by the 2nd page address (5 write
cycles) and data. The address of the second page must be within the second
plane (A18 = 1 for x 8 devices, A17 = 1 for x 16 devices)
provides a description of the multiplane operation while showing the restrictions
Figure 12: Multiplane page program waveform
IPBSY
Section
6.12).
for differences between ONFI
Section 6.3.1: Sequential
Device operations
IPBSY
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, the