HYI39S512160AE-7.5 QIMONDA [Qimonda AG], HYI39S512160AE-7.5 Datasheet - Page 3

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HYI39S512160AE-7.5

Manufacturer Part Number
HYI39S512160AE-7.5
Description
512-Mbit Synchronous DRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1
This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information.
1.1
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C Operating Temperature for HYB...
• -40 to 85 °C Operating Temperature for HYI...
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
• Data Mask for Read / Write control (x4, x8, x16)
1) Max. Frequency CL/
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
Product Type Speed Code
Speed Grade
Max. Clock Frequency
Overview
Features
t
RCD /
t
RP
@CL3
@CL2
f
t
t
t
t
CK3
CK3
AC3
CK2
AC2
3
• Data Mask for Byte Control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 8192 refresh cycles / 64 ms (7.8 µs)
• Random Column Address every CLK (1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface
• Plastic Package : P(G)-TSOPII-54
• RoHS compliant product
–7.5
PC133–333
133
7.5
5.4
10
6
1)
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
Internet Data Sheet
Performance
TABLE 1
Unit
MHz
ns
ns
ns
ns

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