HYI39S512160AE-7.5 QIMONDA [Qimonda AG], HYI39S512160AE-7.5 Datasheet - Page 5

• Manufacturer Part Number: HYI39S512160AE-7.5
• Description: 512-Mbit Synchronous DRAM
• Manufacturer: QIMONDA [Qimonda AG]

2
This chapter contains the pin configuration table and the TSOP package drawing.
2.1
Listed below are the pin configurations sections for the various signals of the SDRAM.
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
Ball No.
Clock Signals x4/ x8/ x16 Organization
38
37
Control Signals x4/ x8/ x16 Organization
18
17
16
19
Address Signals x4/ x8/ x16 Organization
20
21
23
24
25
26
29
30
31
32
33
34
22
35
36
Name
CLK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Configuration
Pin Configuration
Buffer
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Function
Clock Signal CLK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Chip Select
Bank Address Signals 1:0
Address Signal 9:0, Address Signal 10/Auto precharge
5
Ball Configuration of the SDRAM
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
Internet Data Sheet
TABLE 3