HYB18H256321BF QIMONDA [Qimonda AG], HYB18H256321BF Datasheet - Page 9

• Manufacturer Part Number: HYB18H256321BF
• Description: 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.3
2.3.1
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the
chip’s multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions
are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the
assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank
t
1) Action ACTIVATE starts with issuing the command and ends after
2) During action ACTIVATE an ACT command on another bank is allowed considering
3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge.
4) During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge.
6) During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
8) During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on
9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after
Rev. 0.80, 2007-09
09132007-07EM-7OYI
RTW
Current State
ACTIVE
IDLE
POWER DOWN
SELF REFRESH
any time. WR, WR/A, RD and RD/A are always allowed.
must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before t
has to be separated by at least one NOP from the ongoing command. RD is not allowed before or
an ongoing WRITE/A action.
another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to
meet
and
t
t
RTW
WTR
.
have to be taken always into account.
Truth Tables
Function Truth Table for more than one Activated Bank
Ongoing action on bank n
ACTIVATE
WRITE
WRITE/A
READ
READ/A
PRECHARGE
PRECHARGE ALL
POWER DOWN ENTRY
ACTIVATE 1)
POWER DOWN ENTRY
AUTO REFRESH
SELF REFRESH ENTRY
MODE REGISTER SET (MRS)
EXTENDED MRS
POWER DOWN EXIT
SELF REFRESH EXIT
7)
3)
9)
5)
1)
10)
13)
14)
10)
15)
16)
12)
12)
12)
14)
9
t
RCD
.
Possible action in parallel on bank m
ACT, PRE, WRITE, WRITE/A, READ, READ/A
ACT, PRE, WRITE, WRITE/A, READ, READ/A
ACT, PRE, WRITE, WRITE/A, READ
ACT, PRE, WRITE, WRITE/A, READ, READ/A
ACT, PRE, WRITE, WRITE/A, READ, READ/A
ACT, PRE, WRITE, WRITE/A, READ, READ/A
-
-
ACT
-
-
-
-
-
-
-
t
RRD
, a PRE command on another bank is allowed
t
RP
.
t
WTR
is met. RD/A is not allowed during
WTR
Function Truth Table I
is met.
Internet Data Sheet
HYB18H256321BF
6)
256-Mbit GDDR3
TABLE 4
2)
4)
8)
11)
8)
t
RRD
,