DSM2180F315K6 STMICROELECTRONICS [STMicroelectronics], DSM2180F315K6 Datasheet
DSM2180F315K6
Related parts for DSM2180F315K6
DSM2180F315K6 Summary of contents
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... DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) FEATURES SUMMARY Glueless Connection to DSP – Easily add memory, logic, and I/O to DSP 128K Byte Flash Memory – For Bootloading and/or Data Overlay Memory – Programmable Decoding and Paging Logic ...
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... Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Specifying Mem Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Erasing Flash Memory Flash Memory Sector Protect DSM Security Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Decode PLD (DPLD Complex PLD (CPLD) ...
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... Table: CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table: Reset (Reset) Timing Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table: PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . . 57 Table: Assignments – ...
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... I/O pin can be driven by DSP software or AD4 34 PLD logic. PLD and I/O configuration are program- mable by JTAG ISP, just like the Flash memory. The PLD consists of more than 3000 gates and has 16 macro cell registers. Common uses for the AI02857 PLD include chip selects for external devices (i.e. ...
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... EMI levels, and power consumption. DSM memory and logic are “zero-power”, meaning they BUS I/O automatically go to standby between memory ac- cesses or logic input changes, producing low ac- tive and standby current consumption, which is ideal for battery powered products. DSM2180F3 ...
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... DSM device, after which the device is blank and may be used again. The DSP will always have access to Flash memory contents through the 8-bit data port even while the security bit is set. Flash Partitioning ...
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... BDMA, data, & I/O access IOMS respectively (no program memory access, Flash Memory The 1 Mbit (128K x 8) Flash memory is divided into eight equally-sized 16K byte sectors that are indi- vidually selectable through the Decode PLD. Each Flash memory sector can be located at any ad- dress as defined by the user with PSDsoft Ex- press ...
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... DSP software. Decode PLD (DPLD). This is programmable log- ic used to select one of the eight individual Flash memory segments or the group of control registers within the DSM device. The DPLD can also option- ally drive external chip select signals on Port D pins. DPLD input signals include: DSP address and control signals, Page Register outputs, DSM Port Pins, CPLD logic feedback ...
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... DSP at runtime as one of the csiop registers. Its outputs feed directly into the PLDs. The page reg- ister is a powerful feature that allows the DSP to access all 128K Bytes of DSM Flash memory in 16K byte pages. This size matches the 16K loca- tion data overlay window the ADSP-218X family. ...
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... CPLD output (External Chip Select). Does not consume Output Macrocells. 4. Pin PD1 can optionally be configured as CLKIN, a common clock input to PLD. 5. Pin PD2 can optionally be configured as CSI, an active low Chip Select Input to select Flash memory. Flash memory is disabled to conserve more power when CSI is logic high. Can PD0-2 I/O connect CSI to ADSP-218X PWDACK output signal ...
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... DSM pins are multipurpose. The scheme illustrat ideal for a design that needs fast JTAG ISP, Eight additional general I/O with PLD capability, access to Flash memory as Byte DMA or as Data Overlay memory, and the DSP uses Power Down mode. If your design needs more I/O, or Byte DMA ...
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DSM2180F3 Figure 6. Typical Connections 12/63 ...
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... Flash memory programming algorithm). A DMA channel is not optimum for this scenario since the channel must be initialized on each byte access. That is why the 128K Bytes of Flash memory also lie in DSP Data Overlay Memory space as described next. Data Overlay Memory Address Space. All ...
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... DSM2180F3 Figure 7. Typical System Memory Map 14/63 ...
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... PSDsoft Express ate Hardware Definition Language (HDL) state- Figure 8. HDL Statements Generated from PSDsoft Express to Implement Memory Map csiop = ((address >= ^h0000) & (address <= ^h00FF) & (!_ioms & _dms & _bms)); fs0 = ((address >= ^h0000) & (address <= ^h3FFF) & (_ioms & _dms & !_bms)) # ((page == 0) & ...
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... DSM2180F3 TM Figure 9. PSDsoft Express 16/63 Memory Mapping AI03779 ...
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... Select I/O Port). Table 4 lists the 27 registers and their offsets (in hex) from the csiop base address needed to access individual DSM control and status registers. The DSP will access these registers in I/O memory space using its Table 4. CSIOP Registers and their Offsets (in hex) Register Name Port B ...
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... If the DSP accesses the DSM in BDMA mode, then the DSP BDMA channel must be initialized and run for each byte (or block of bytes) read from Flash memory or it must initialize the DMA channel for each byte writ- ten to Flash memory. Alternatively, if the DSP ac- ...
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... Note: 1. All values are in hexadecimal Don’t Care 2. A desired internal Flash memory sector select signal (FS0 - FS7) must be active for each write or read cycle. Only one of FS0 - FS7 will be active at any given time depending on the address presented by the DSP and the memory mapping defined in PSDsoft Ex- press. FS0 - FS7 are active high logic internally. 3. DSP addresses A17 through A12 are Don’ ...
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... Flag Flag these tasks and are defined in Table 6. The status bits can be read as many times as needed. For Flash memory, the DSP can perform a read operation to obtain these status bits while an Erase or Program instruction sequence is being executed by the embedded algorithm. See the ...
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... Programming Flash Memory When a byte of Flash memory is programmed, in- dividual bits are programmed to logic 0. You can- not program a bit in Flash memory to a logic 1 once it has been programmed to a logic 0. A bit must be erased to logic 1, and programmed to log That means Flash memory must be erased prior to being programmed ...
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... It is suggested (as with all Flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 10 still applies ...
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... Flag (DQ5) bit returns there has been an Erase Failure (maximum number of Erase cycles have been executed not necessary to program the memory with 00h because the device automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction se- quence, the Flash memory does not accept any in- struction sequences ...
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... Table 7. Sector Protection/Security Bit Definition – Flash Protection Register Bit 7 Bit 6 Bit 5 Sec7_Prot Sec6_Prot Sec5_Prot Note: 1. Bit Definitions: Sec<i>_Prot 1 = Flash memory sector <i> is write protected. Sec<i>_Prot 0 = Flash memory sector <i> is not write protected. Table 8. Security Bit Definition Bit 7 Bit 6 Bit 5 Security_Bit not used not used Note: 1. Bit Definitions Security Bit in device has been set ...
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... PG7) are inputs to the DPLD decoder and can be included in the Sector Select ( FS0-FS7 ) equa- tions. See Figure 12. If memory paging is not needed not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic ...
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... DSM2180F3 The DPLD performs address decoding, and gen- erates select signals for internal and external com- ponents, such as memory, registers, and I/O ports. The DPLD can generates External Chip Select (ECS0-ECS2) signals on Port D. The CPLD can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic ...
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... The DPLD, shown in Figure 14, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: 8 Flash memory Sector Select ( FS0-FS7 ) signals with three product terms each Figure 14. DPLD Logic Array (INPUTS PORTS (PORT A,B,C) MCELLAB ...
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DSM2180F3 COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. See application note AN1171 for details on how to ...
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The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block ...
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... Port Input 30/63 Loading and Reading the Output Macrocells (OMCs). Each of the two OMC blocks (8 OMCs each) occupies a memory location in the DSP ad- dress space, as defined in the csiop block MCELLAB0-7 and MCELLBC0-7 (see Table 4). The flip-flops in each of the 16 OMCs can be load- ed from the data bus by a DSP. Loading the OMCs with data from the DSP takes priority over internal functions ...
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The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Out- put Macrocells (OMC). The default ...
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... DSP address, data, and control signals connect directly to the DSM device. See Figure 6 for typical connections. DSP address, data and control signals are routed to Flash memory, I/O control ( csiop ), OMCs, and IMCs within the DMS. The DSP address range for each of these components is specified in PSDsoft TM Express ...
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Direction Registers, and port pin input are all connected to the Port Data Buffer (PDB). The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array ...
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DSM2180F3 port. The three Port Configuration Registers (PCR), are shown in Table 12. Default is logic 0. Table 12. Port Configuration Registers (PCR) Register Name Port Data In B,C,D Data Out B,C,D Direction B,C,D 1 B,C,D Drive Select Note: 1. ...
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Table 16. Drive Register Pin Assignment Drive Bit 7 Bit 6 Register Open Open Port B Drain Drain Open Open Port C Drain Drain 1 1 Port Note Not Applicable. Figure 20. Port B ...
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DSM2180F3 Figure 21. Port C Structure DATA OUT REG MCELLBC [ 7:0 ] READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD - INPUT Port C – Functionality and ...
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... DATA IN Q CPLD - INPUT PSD Chip Select Input (CSI, PD2). Driving this signal logic High disables the Flash memory, putting it in standby mode. External Chip Select. The DPLD also provides three External Chip Select outputs (ESC0-2) on Port D pins that can be used to select external de- vices as defined in PSDsoft Express ...
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DSM2180F3 Figure 23. Port D External Chip Select Signals PT0 PT1 PT2 38/63 ENABLE (.OE) POLARITY BIT ENABLE (.OE) POLARITY BIT ENABLE (.OE) POLARITY BIT DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 ...
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... POWER MANAGEMENT The device offers configurable power saving op- tions. These options may be used individually or in combinations, as follows: All memory blocks in the device are built with zero-power management technology. Zero- power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current) ...
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... CSI and the PMMR2 register. Note: CNTL0 and CNTL1 (DSP nently routed to the Flash memory array and can- not be blocked from the array by the PMMR registers (that’s why WR and RD signals do not have to be specified in PSDsoft Express for Flash memory segment chip-select equations for FS0 - FS7) ...
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... OPR through the JTAG signals on Port C. This serial in- terface allows programming of the entire DSM de- vice or subsections (i.e. only Flash memory but not the PLDs) without and participation of the DSP. A blank DSM device soldered to a circuit board can be completely programmed seconds. ...
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... This signal goes Low (active) when an Error condition occurs. TSTAT behaves the same as Ready/Busy de- scribed previously. the device is in Read mode (Flash memory con- tents can be read). memory Program or Erase cycles are in progress. TSTAT and TERR can be configured as open- drain type signals with PSDsoft Express. This fa- ...
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... V ISP signals on your circuit board. Initial Delivery State When delivered from ST, the device has all bits in the memory and PLDs erased to logic 1. The DSM on all JTAG- Configuration Register bits are set to 0. The code, CC configuration, and PLD logic are loaded using the programming procedure ...
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... Also, the supply power is considerably different if the Turbo bit is 0. The AC power component gives the PLD and Flash memory a mA/MHz specification. Figure 25 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo bit is 0 ...
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...
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DSM2180F3 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests ...
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Table 25. AC Symbols for PLD Timing Signal Letters A Address Input C CEout Output D Input Data E E Input N Reset Input or Output P Port Signal Output Q Output Data R RD Input (read) S Chip Select ...
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... STBY CSI >V –0.3 V (Notes CC V < V < 0.45 < V < V OUT CC PLD_TURBO = Off MHz (Note ) PLD_TURBO = On MHz During Flash memory Write/ Erase Only Read Only MHz is valid at or below 0.2V –0.1. V IL1 CC IH1 Min. Typ. Max –0.5 0.8 0. ...
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Table 27. CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/Feedback CPLD Combinatorial Output CPLD Input to CPLD Output t EA Enable CPLD Input to CPLD Output t ER Disable CPLD Register Clear or Preset t ARP Delay ...
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DSM2180F3 Table 28. CPLD Macrocell Synchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f Internal Feedback MAX (f ) CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock ...
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Figure 29. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Figure 30. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 31. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Figure 32. Asynchronous Clock Mode ...
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DSM2180F3 Table 30. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL t NIB Input to Combinatorial Delay INO Note: 1. Inputs ...
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Table 31. Read Timing Symbol Parameter t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV Data Valid 8-Bit Bus RLQV t RD Data Hold Time RHQX t RD Pulse Width RLRH t ...
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... Note: 1. Any input used to select an internal DSM function. 2. Assuming data is stable before active write signal. 3. Assuming write is active before data becomes valid. 4. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal DSM memory. Figure 35. Write Timing ADDRESS ...
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... Power On Reset Active Low Time NLNH–PO t RESET High to Operational Device OPR Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode. Figure 36. Reset (RESET) Timing V (min ...
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DSM2180F3 Table 35. ISC Timing Symbol t Clock (TCK, PC1) Frequency (except for PLD) ISCCF t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock (TCK, PC1) Low Time (except for PLD) ISCCL t Clock (TCK, PC1) Frequency ...
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PACKAGE MECHANICAL PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular M PLCC-B Note: Drawing is not to scale. PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular Symbol Typ ...
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DSM2180F3 Table 36. Assignments – PLCC52 Pin No. Pin Assignments 1 GND 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 15 V ...
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PQFP52 - 52 lead Plastic Quad Flatpack Ne N QFP Note: Drawing is not to scale. PQFP52 - 52 lead Plastic Quad Flatpack Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 ...
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DSM2180F3 Table 37. Pin Assignments – PQFP52 Pin No. Pin Assignments 1 PD2 2 PD1 3 PD0 4 PC7 5 PC6 6 PC5 7 PC4 GND 10 PC3 11 PC2 12 PC1 13 PC0 14 PA7 15 ...
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... PART NUMBERING Table 38. Ordering Information Scheme Example: Device Type DSM21 = DSP System Memory for ADSP-21XX Family DSP Applicability 80 = Analog Devices ADSP-218X family Memory Density Mbit x 8 (128K Bytes) Operating Voltage (Vcc) blank = 5V ±10 3.3V ± 10% Access Time nsec 15 = 150 nsec ...
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DSM2180F3 REVISION HISTORY Table 39. Document Revision History Date Rev. 20-Jun-2001 1.0 Document written 06-Nov-2001 1.1 Information on the 3.3V±10% range removed to a separate data sheet 17-Dec-2001 1.2 PQFP52 package mechanical data updated 62/63 Description of Revision ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...