AT45DB321C-RI ATMEL [ATMEL Corporation], AT45DB321C-RI Datasheet - Page 15

• Manufacturer Part Number: AT45DB321C-RI
• Description: 32 MEGABIT 2.7 VOLT DATAFLASH
• Manufacturer: ATMEL [ATMEL Corporation]

Power-on/Reset State
System
Considerations
3387B–DFLSH–9/04
When power is first applied to the device, or when recovering from a reset condition, the
device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance
state, and a high-to-low transition on the CS pin will be required to start a valid instruc-
tion. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge
of CS by sampling the inactive clock state. After power is applied and V
mum datasheet value, the system should wait 20 ms before an operational mode
(DataFlash) is started.
The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip
select CS pins. These signals must rise and fall monotonically and be free from noise.
Excessive noise or ringing on these pins can be misinterpreted as multiple edges and
cause improper operation of the device. The PC board traces must be kept to a mini-
mum distance or appropriately terminated to ensure proper operation. If necessary,
decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more
important. A key element of any voltage regulation scheme is its current sourcing capa-
bility. Like all Flash memories, the peak current for DataFlash occur during the
programming and erase operation. The regulator needs to supply this peak current
requirement. An under specified regulator can cause current starvation. Besides
increasing system noise, current starvation during programming or erase can lead to
improper operation and possible data corruption.
For applications that require random modifications of data within a sector, please refer
to “Auto Page Rewrite” on page 6.
It is recommended that the RDY/BUSY bit of status register or the RDY/BUSY pin be
monitored in order to minimize the erase and programming time.
Atmel C generation DataFlash utilizes a sophisticated adaptive algorithm during erase
and programming to maximize the endurance over the life of the device. The algorithm
uses a verification mechanism to check if the memory cells have been erased or pro-
grammed successfully. If the memory cells were not erased or programmed, the
algorithm loops back and erases or programs the memory cells again. The process will
continue until the device is erased or programmed successfully.
The erase and programming operations are internally self-timed and fixed timing is not
recommended.
AT45DB321C [Preliminary]
CC
is at the mini-
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