HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 12

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HYB18T512161B2F-20/25

Manufacturer Part Number
HYB18T512161B2F-20/25
Description
512-Mbit x16 DDR2 SDRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1) w = write only register bits
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Field
AL
R
DIC
DLL
Field
BA1
BA0
A
SRF
A
TT
Bits
14
13
[12:8]
7
[6:3]
Bits
[5:3]
6,2
1
0
Type
reg. addr., Bank Address [1]
w
w
w
Type
1)
1)
Description
1
Bank Address [0]
0
Address Bus
00000
Address Bus, High Temperature Self Refresh Rate for
0
1
Address Bus
0000
B
B
B
B
Description
Additive Latency
Note: All other bit combinations are illegal.
000
001
010
011
100
101
110
Nominal Termination Resistance of ODT
00
01
10
11
Off-chip Driver Impedance Control
0
1
DLL Enable
0
1
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
BA1 Bank Address
BA0 Bank Address
B
A7 disable
A7 enable
A Address bits
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10
AL 0
AL 1
AL 2
AL 3
AL 4
AL 5
AL 6
RTT ∞ (ODT disabled)
RTT 75 Ohm
RTT 150 Ohm
RTT 50 Ohm
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
DLL Disable
A Address bits
2)
12
512-Mbit Double-Data-Rate-Two SDRAM
T
CASE
HYB18T512161B2F–20/25
> 85°C
Internet Data Sheet
TABLE 8
B
)

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