HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 25

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

5.7
5.7.1
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Speed Grade
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” according
to
level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter
t
RAS.MAX
Chapter 7.1
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
7.3.
only.
AC Characteristics
Speed Grade Definitions
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
@ CL = 7
V
REF
V
stabilizes. During the period before
TT
. See
Symbol
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
RAS
RC
RCD
RP
Chapter 7.1
–20
Min.
5
3.75
3
2.5
2.0
45
60
15
15
25
for the reference load for timing measurements.
Max.
8
8
8
8
8
70k
—
—
—
V
REF
512-Mbit Double-Data-Rate-Two SDRAM
stabilizes, CKE = 0.2 x
5
3.75
3
2.5
—
45
60
15
15
–25
Min.
Max.
8
8
8
8
—
70k
—
—
—
HYB18T512161B2F–20/25
Speed Grade Definition
V
DDQ
Internet Data Sheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
is recognized as low.
TABLE 28
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.