HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 5

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

2
2.1
The chip configuration of a DDR2 SDRAM is listed by function in
columns are explained in
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Ball#
Clock Signals
J8
K8
K2
Control Signals
K7
L7
K3
L8
Address Signals
Configuration
Chip Configuration
CKE
Name
CK
CK
RAS
CAS
WE
CS
Table 3
and
Type
I
I
I
I
I
I
I
Ball
Table 4
respectively. The ball numbering for the FBGA package is depicted in
SSTL
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Clock Signal CK, Complementary Clock Signal CK
Note: CK and CK are differential system clock inputs. All address
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
5
Table
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-
Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit,
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are
disabled during power-down
2. The abbreviations used in the Ball# and Buffer Type
V
REF
V
has become stable during power-on and
REF
512-Mbit Double-Data-Rate-Two SDRAM
must be maintained to this input. CKE must
Chip Configuration of DDR2 SDRAM
HYB18T512161B2F–20/25
Internet Data Sheet
TABLE 2
Figure
1.