HYB18T512800AF QIMONDA [Qimonda AG], HYB18T512800AF Datasheet - Page 12

• Manufacturer Part Number: HYB18T512800AF
• Description: 240-Pin Fully-Buffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.
3.1
The Advanced Memory Buffer will perform the following FB-
DIMM channel functions:
• Supports channel initialization procedures as defined in
• Supports the forwarding of southbound and northbound
• If the AMB resides on the last DIMM in the channel, the
Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower
speed tester access to DRAM pins through the FB-DIMM I/O
pins. This allows the tester to send an arbitrary test pattern to
the DRAMs. Transparent mode only supports a maximum
DRAM frequency equivalent to DDR2 400. Transparent mode
functionality:
DDR2 SDRAM Interface
• Supports DDR2 at speeds of 533, 667MT/s
• Supports 256Mb, 512Mb and 1Gb devices in x4 and x8
3.2
Figure 2
interfaces. They consist of two FB-DIMM links, one DDR2
channel and an SMBus interface. Each FB-DIMM link
connects the Advanced Memory Buffer to a host memory
Rev. 1.2, 2006-11
03292006-GUME-ERC3
the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame
boundaries, verify channel connectivity, and identify AMB
DIMM position.
frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the
return data into the northbound frames.
AMB initializes northbound frames.
configurations
illustrates the Advanced Memory Buffer and all of its
Basic Functionality
Advanced Memory Buffer Functionality
Interfaces
12
• Detects errors on the channel and reports them to the host
• Support the FB-DIMM configuration register set as defined
• Acts as DRAM memory buffer for all read, write, and
• Provides a read buffer FIFO and a write buffer FIFO.
• Supports an SMBus protocol interface for access to the
• Provides logic to support MEMBIST and IBIST Design for
• Provides a register interface for the thermal sensor and
• Functions as a repeater to extend the maximum length of
• Reconfigures FB-DIMM inputs from differential high speed
• These inputs directly control DDR2 Command/Address
• Uses low speed direct drive FB-DIMM outputs to bypass
• 72-bit DDR2 SDRAM memory array
controller or an adjacent FB-DIMM. The DDR2 channel
supports direct connection to the DDR2 SDRAMs on a Fully
Buffered DIMM.
memory controller.
in the register chapters.
configuration accesses addressed to the DIMM.
AMB configuration registers.
Test functions.
status indicator.
FB-DIMM Links.
link receivers to two single ended lower speed receivers
(~200 MHz)
and input data that is replicated to all DRAMs
high speed Parallel/Serial circuitry and provide test results
back to tester
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
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