HYB18T512800AF QIMONDA [Qimonda AG], HYB18T512800AF Datasheet - Page 26

• Manufacturer Part Number: HYB18T512800AF
• Description: 240-Pin Fully-Buffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

Rev. 1.2, 2006-11
03292006-GUME-ERC3
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
t
Write Recovery Values Supported (WR)
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
t
t
t
t
t
t
t
t
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
t
T
Psi(T-A) DRAM
∆
∆
∆
∆
∆
CAS.MIN
WR.MIN
RCD.MIN
RRD.MIN
RP.MIN
RAS
RAS.MIN
RC.MIN
RFC.MIN
RFC.MIN
WTR.MIN
RTP.MIN
REFI
CASE.MAX
T
T
T
T
T
0
2Q
2P
3N
4R
(DT0) DRAM
and
(avg. SDRAM Refresh Period)
(DT2P) DRAM
(DT3N) DRAM
(DT4R) / ∆
(DT2Q) DRAM
(min. Row Precharge Time)
(min. Active to Active / Refresh Time)
(Write Recovery Time)
(min. CAS Latency Time)
(min. Active to Precharge Time)
LSB (min. Refresh Recovery Time Delay)
MSB (min. Refresh Recovery Time Delay)
(min. Internal Read to Precharge Cmd Delay)
(min. RAS# to CAS# Delay)
(min. Row Active to Row Active Delay)
(min. Internal Write to Read Cmd Delay)
t
RC
Delta / ∆
Extension
T
4R4W
T
4R4W
Sign (DT4R4W) DRAM
Delta
26
512MB
×72
1 Rank (×8)
PC2–5300F–555
Rev. 1.1
HEX
3C
42
72
50
3C
1E
3C
00
F0
A4
01
1E
1E
03
07
01
53
78
48
2E
26
4A
3C
B4
C2
26
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
1 GByte
×72
2 Ranks (×8)
PC2–5300F–555
Rev. 1.1
HEX
3C
42
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
1E
03
07
01
C2
53
78
48
2E
26
26
4A
3C
Internet Data Sheet
2 GByte
×72
2 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
3C
42
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
1E
03
07
01
C2
53
78
48
2E
26
26
4A
3C