HYB18T512800AF QIMONDA [Qimonda AG], HYB18T512800AF Datasheet - Page 20

• Manufacturer Part Number: HYB18T512800AF
• Description: 240-Pin Fully-Buffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27
7. Termination is referenced to V
Rev. 1.2, 2006-11
03292006-GUME-ERC3
Parameter
MemBIST
Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
Electrical Idle
DRAM Idle (0 BW)
Primary channel Disabled
Secondary channel Disabled
CKE low. Command and Address lines Floated
DRAM clock active, ODT and CKE driven low
Ω
termination for command, address, and clocks, and 47
TT
= V
DD
/ 2.
20
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
Ω
termination for control.
Internet Data Sheet
Symbol
I
I
I
I
CC_MEMBIST
DD_MEMBIST
CC_EI
DD_EI