HT6256DB HONEYWELL [Honeywell Solid State Electronics Center], HT6256DB Datasheet - Page 5

• Manufacturer Part Number: HT6256DB
• Description: HIGH TEMPERATURE 32K x 8 STATIC RAM
• Manufacturer: HONEYWELL [Honeywell Solid State Electronics Center]

READ CYCLE AC TIMING CHARACTERISTICS (1)
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels
(2) Typical operating conditions: VDD=5.0 V, TA=25 C.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 225 C.
(4) External control of Chip Enable (CE) is available only in other package options.
Symbol
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TGLQV
TGLQX
TGHQZ
TEHQV
TEHQX
TELQZ
shown in the Tester AC Timing Characteristics table, capacitive output loading C
TSHQZ and TGHQZ. For C
ADDRESS
NCS
DATA OUT
CE
NOE
Parameter
Address Read Cycle Time
Address Access Time
Address Change to Output Invalid Time
Chip Select Access Time
Chip Select Output Enable Time
Chip Select Output Disable Time
Output Enable Access Time
Output Enable Output Enable Time
Output Enable Output Disable Time
Chip Enable Output Access Time (4)
Chip Enable Output enable Time (4)
Chip Enable Output Disable Time (4)
(NWE = high)
L
>50 pF, derate access times by 0.02 ns/pF (typical).
IMPEDANCE
HIGH
T
T
EHQX
EHQV
T
AVQV
T
T
T
T
T
SLQV
SLQX
AVAVR
GLQX
GLQV
5
DATA VALID
L
>50 pF, or equivalent capacitive output loading C
T
AXQX
Typical (2)
17
10
4
Worst Case (3)
T
T
50
ELQZ
Min
3
5
0
5
SHQZ
T
GHQZ
Max
50
50
20
15
15
25
10
HT6256
L
=5 pF for
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns