E28F004BX-B120 INTEL [Intel Corporation], E28F004BX-B120 Datasheet - Page 20

• Manufacturer Part Number: E28F004BX-B120
• Description: 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY
• Manufacturer: INTEL [Intel Corporation]

28F400BX-T B 28F004BX-T B
NOTES
1 Bus operations are defined in Tables 1 2 3
2 IA
3 SRD
4 IID
Following the Intelligent Identifier Command two read operations access manufacturer and device codes
5 BA
6 WA
WD
7 Either 40H or 10H commands is valid
8 When writing commands to the device the upper data bus DQ
to avoid burning additional current
Invalid Reserved
These are unassigned commands It is not recom-
mended that the customer use any command other
than the valid commands specified above Intel re-
serves the right to redefine these codes for future
functions
Read Array (FFH)
This single write command points the read path at
the array If the host CPU performs a CE
controlled read immediately following a two-write se-
quence that started the WSM then the device will
output status register contents If the Read Array
command is given after Erase Setup the device is
reset to read the array A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup
Intelligent Identifier (90H)
After this command is executed the CUI points the
output path to the Intelligent Identifier circuits Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A
other address inputs are ignored)
20
Read Array
Intelligent Identifier
Read Status Register
Clear Status Register
Erase Setup Erase Confirm
Word Byte Write Setup Write
Erase Suspend Erase Resume
Alternate Word Byte
Write Setup Write
e
e
e
e
e
Data to be written at location WD
e
Identifier Address 00H for manufacturer code 01H for device code
Intelligent Identifier Data
Address within the block being erased
Address to be written
Data read from Status Register
Command
0
is used in this mode all
Cycles
Req’d
Bus
1
3
2
1
2
2
2
2
Table 4 Command Definitions
Notes
2 4
6 7
6 7
8
1
3
5
OE
Operation Address Data Operation Address Data
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Read Status Register (70H)
This is one of the two commands that is executable
while the state machine is operating After this com-
mand is written a read of the device will output the
contents of the status register regardless of the ad-
dress presented to the device
The device automatically enters this mode after pro-
gram or erase has completed
Clear Status Register (50H)
The WSM can only set the Program Status and
Erase Status bits in the status register it can not
clear them Two reasons exist for operating the
status register in this fashion The first is a synchro-
nization The WSM does not know when the host
CPU has read the status register therefore it would
not know when to clear the status bits Secondly if
the CPU is programming a string of bytes it may be
more efficient to query the status register after pro-
gramming the string Thus if any errors exist while
programming the string the status register will return
the accumulated error status
8
–DQ
15
WA
WA
BA
e
X
X
X
X
X
X (28F400BX-only) which is either V
FFH
90H
70H
50H
20H
40H
B0H
10H
Read
Read
Write
Write
Write
Write
Second Bus Cycle
WA
WA
BA
IA
X
X
CC
or V
SRD
D0H
D0H
WD
WD
IID
SS