AT17LV002A-10BJC ATMEL [ATMEL Corporation], AT17LV002A-10BJC Datasheet

AT17LV002A-10BJC

Manufacturer Part Number

AT17LV002A-10BJC

Description

FPGA Configuration EEPROM Memory

Manufacturer

ATMEL [ATMEL Corporation]

Datasheet

1.AT17LV002A-10BJC.pdf (24 pages)

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Features

•

Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-

to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The

AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-

lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The

AT17LV series Configurators uses a simple serial-access procedure to configure one

or more FPGA devices. The user can select the polarity of the reset function by pro-

gramming four EEPROM bytes. These devices also support a write-protection

mechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard program-

mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Table 1. AT17LV Series Packages

Notes:

Package

8-lead LAP

8-lead PDIP

8-lead SOIC

20-lead PLCC

20-lead SOIC

44-lead PLCC

44-lead TQFP

EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,

2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

Supports both 3.3V and 5.0V Operating Voltage Applications

In-System Programmable (ISP) via Two-Wire Bus

Simple Interface to SRAM FPGAs

Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX

Devices, Lucent ORCA

Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

Very Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and

44-lead TQFP Packages

Emulation of Atmel’s AT24CXXX Serial EEPROMs

Low-power Standby Mode

High-reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for

Commercial Parts (at 70°C)

1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-

2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the

3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.

lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi-

ble to use an 8-lead LAP package instead.

AT17LV512/010/002 devices.

AT17LV128/

AT17LV256

AT17LV65/

Yes

, Xilinx XC3000

–

(2)

Use 8-lead LAP

AT17LV512/

AT17LV010

™

Yes

, XC4000

Yes

–

(2)

(1)

™

, XC5200

Use 8-lead LAP

AT17LV002

Yes

™

–

, Spartan

(2)

(1)

, Virtex

AT17LV040

, APEX

Yes

(3)

–

™

FPGAs

FPGA

Configuration

EEPROM

Memory

AT17LV65

AT17LV128

AT17LV256

AT17LV512

AT17LV010

AT17LV002

AT17LV040

3.3V and 5V

System Support

Rev. 2321E–CNFG–06/03

Related parts for AT17LV002A-10BJC

AT17LV002A-10BJC Summary of contents

Page 1

Features • EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • ...

Page 2

Pin Configuration (WP (WP AT17LV65/128/256/512/010/002/040 2 8-lead LAP DATA 1 8 VCC CLK 2 7 SER_EN (1) (WP ) RESET/ CEO (A2 GND 8-lead SOIC DATA 1 8 CLK 2 7 (1) ) RESET/OE 3 ...

Page 3

AT17LV65/128/256/512/010/002/040 (1) 20-lead SOIC DATA CLK RESET/ GND 10 11 Note: 1. This pinout only ...

Page 4

AT17LV65/128/256/512/010/002/040 4 44 PLCC ( TQFP ...

Page 5

Block Diagram SER_EN (2) WP1 (2) WP2 POWER ON RESET Device Description 2321E–CNFG–06/03 AT17LV65/128/256/512/010/002/040 (2) (1) READY Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. The control signals for ...

Page 6

Pin Description AT17LV65/ AT17LV128/ AT17LV256 8 DIP/ LAP/ 20 Name I/O SOIC PLCC I/ DATA CLK WP1 I – – RESET/ WP2 GND 5 10 CEO ...

Page 7

CE GND CEO A2 READY SER_EN V CC 2321E–CNFG–06/03 AT17LV65/128/256/512/010/002/040 Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables ...

Page 8

FPGA Master Serial Mode Summary Control of Configuration Cascading Serial Configuration EEPROMs AT17LV Series Reset Polarity Programming Mode Standby Mode AT17LV65/128/256/512/010/002/040 8 The I/O and logic functions of any SRAM-based FPGA are established by a configura- tion program. The program ...

Page 9

Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering Temp. (10 sec. @ ...

Page 10

DC Characteristics V = 3.3V ± 10% CC Symbol Description V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage ( Low-level Output Voltage ( High-level Output Voltage (I OH ...

Page 11

AC Characteristics CE RESET/OE CLK T CE DATA AC Characteristics when Cascading RESET/OE CE CLK T LAST BIT DATA T CEO 2321E–CNFG–06/03 AT17LV65/128/256/512/010/002/040 T SCE CAC CDF T OCK OCE T SCE T ...

Page 12

AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK OH ...

Page 13

AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T ...

Page 14

Thermal Resistance Coefficients Package Type 8CN4 Leadless Array Package (LAP) 8P3 Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline 8S1 (SOIC) Plastic Leaded Chip Carrier 20J (PLCC) Plastic Gull Wing Small Outline 20S2 (SOIC) Thin Plastic Quad Flat ...

Page 15

Figure 1. Ordering Code Voltage Size (Bits) 3.0V to 5.5V 65 128 256 512 010 002 040 8CN4 8-lead mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" ...

Page 16

Ordering Information Memory Size (1) 64-Kbit AT17LV65-10CC AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC AT17LV65-10CI AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI (1) 128-Kbit AT17LV128-10CC AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10CI AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI (1) 256-Kbit AT17LV256-10CC AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10CI AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI ...

Page 17

Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E Top View 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R 2321E–CNFG–06/03 AT17LV65/128/256/512/010/002/040 D Side View ...

Page 18

PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the ...

Page 19

SOIC 3 Top View e D Side View End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2325 Orchard Parkway San Jose, CA ...

Page 20

PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension ...

Page 21

SOIC Top View e D Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. ...

Page 22

TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. ...

Page 23

PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

Page 24

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem ...

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