AT17LV002A-10BJC ATMEL [ATMEL Corporation], AT17LV002A-10BJC Datasheet - Page 21

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AT17LV002A-10BJC

Manufacturer Part Number
AT17LV002A-10BJC
Description
FPGA Configuration EEPROM Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
20S2 – SOIC
2321E–CNFG–06/03
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
R
0.15 mm (0.006") per side.
(0.010") per side.
(0.024") per side.
2325 Orchard Parkway
San Jose, CA 95131
e
Top View
Side View
D
TITLE
20S2, 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
N
1
E
b
AT17LV65/128/256/512/010/002/040
A
H
SYMBOL
A
A1
b
C
D
E
H
L
e
A1
C
End View
0.0926
0.0040
0.0130
0.0091
0.4961
0.2914
0.3940
0.0160
(Unit of Measure = inches)
COMMON DIMENSIONS
MIN
0.050 BSC
NOM
DRAWING NO.
0.1043
0.0118
0.0200
0.0125
0.5118
0.2992
0.4190
0.050
MAX
20S2
NOTE
4
1
2
3
1/9/02
REV.
A
21

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