CP2400 SILABS [Silicon Laboratories], CP2400 Datasheet - Page 35

• Manufacturer Part Number: CP2400
• Description: 128/64 SEGMENT LCD DRIVER
• Manufacturer: SILABS [Silicon Laboratories]

6.1.
The SPI interface supports 6 commands which provide access to all internal registers and RAM. The six
commands are listed in Table 6.1. Detailed information on the SPI interface including bus timing can be found in
Section “14. Serial Peripheral Interface (SPI)” on page 101.
Figure 6.2 shows a typical SPI transfer used to access internal registers or RAM. The first three bytes of the
transfer are interpreted as COMMAND, ADDRH, and ADDRL. On a read, the fourth byte is a wait state in which the
SPI shift register contents are ignored; starting with the fifth byte, data transfer begins. On a write, the fourth byte is
the first data byte. The direction of data transfer depends on the specified command. The SPI transaction ends
when NSS is de-asserted.
Note: Using the RAMREAD command to read an address outside the 0x400–0x4FF range will result in a data value of 0xDE.
REGPOLL
REGREAD
REGSET
REGWRITE
RAMREAD
RAMWRITE
Accessing Internal Registers and RAM over the SPI Interface
Read:
Write:
Command
COMMAND
COMMAND
ADDRH
ADDRH
OPCODE
0x01
0x02
0x03
0x06
0x08
0x04
ADDRL
ADDRL
Table 6.1. SPI Command Set
Writes one or more bytes to a single register. Used for generating a
Reads one or more bytes from registers with sequential addresses.
waveform on a GPIO pin or updating the SmaRTClock registers.
Writes one or more bytes to registers with sequential addresses.
Figure 6.2. SPI Transfer
Reads data from a single register. Used for polling a status bit.
Reads one or more bytes from sequential RAM locations.
Writes one or more bytes to sequential RAM locations.
Rev. 1.0
DATA 0
WAIT
Description
DATA 0
DATA 1
CP2400/1/2/3
DATA N
DATA N
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