CP2400 SILABS [Silicon Laboratories], CP2400 Datasheet - Page 62

• Manufacturer Part Number: CP2400
• Description: 128/64 SEGMENT LCD DRIVER
• Manufacturer: SILABS [Silicon Laboratories]

CP2400/1/2/3
10.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic
All Port I/Os configured for digital, open-drain operation are capable of interfacing to digital logic operating at a
supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8 to 2.2 V, the
I/O may also interface to digital logic operating between 3.0 to 3.6 V. An external pull-up resistor to the higher
supply voltage is typically required for most systems.
Important Notes:
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10.1.4. Increasing Port I/O Drive Strength
Port I/O digital output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRIVE registers. See Table 3.2 on page 13 for the difference
in output drive strength between the two modes.
10.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins are multi-function and may be used for multiple purposes. The following process can be used to
assign GPIO pins to their appropriate function.
1. Determine the pins to be used for the LCD function. These pins need to be configured for Analog I/O.
2. Any remaining unused pins may be used for GPIO or Port Match. These pins need to be configured for Digital I/
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When interfacing to a signal that is between 4.5 and 5.25 V, the maximum clock frequency that may be input on
a GPIO pin is 12.5 MHz. The exception to this rule is when routing an external CMOS clock to P0.3, in which
case a signal up to 25 MHz is valid as long as the rise time (10% to 90%) is shorter than 1.8 ns.
When the supply voltage is less than 2.8 V and interfacing to a signal that is between 3.0 and 3.6 V, the
maximum clock frequency that may be input on a GPIO pin is 3.125 MHz. The exception to this rule is when
routing an external CMOS clock to P0.3, in which case a signal up to 25 MHz is valid as long as the rise time
(10% to 90%) is shorter than 1.2 ns.
In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150 µA to
flow into the Port pin when the supply voltage is between (VDD_MCU/DC+ plus 0.4 V) and (VDD_MCU/DC+
plus 1.0 V). Once the Port pad voltage increases beyond this range, the current flowing into the Port pin is
minimal.
These guidelines only apply to multi-voltage interfaces. Port I/Os may always interface to digital logic operating
at the same supply voltage.
O. Note: ULP Port Match is only available on a limited number of pins. See Section “9.7. Port Match
Functionality in the Ultra Low Power Modes” on page 56 for more details. All Port
I/O with the exception of P3.3–P4.3 must be configured to Analog mode prior to entering ULP Mode.
Rev. 1.0