ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 58

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

ADP1046
Bits
2
1
0
Table 45. Register 0x2D—PGOOD Debounce and Pin Polarity Settings
Bits
[7:6]
[5:4]
3
2
1
0
Table 46. Register 0x2E—Modulation Limit
Bits
7
[6:0]
Bit Name
Reserved
Disable light load
during soft start
Force soft start
filter
Bit Name
PGOOD1 turn-on
debounce
PGOOD2 turn-on
debounce
PGOOD2 flags
FLAGIN polarity
GATE polarity
PSON polarity
Bit Name
Full-bridge mode
Modulation limits
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Set this bit to zero for normal operation.
0 = allow switching to light load mode filter during soft start.
1 = never switch to light load mode filter during soft start.
0 = use normal mode filter or soft start filter, depending on the OrFET status. If regulating from
VS3 (OrFET on), the normal mode filter is used. If regulating from VS1 (OrFET off ), the soft start
filter is used.
1 = use soft start filter as the initial filter regardless of OrFET status.
Description
These bits set the debounce time before the PGOOD1 pin and flag are set. This debounce time
starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD1 is always
immediate (no debounce).
Bit 7
0
0
1
1
These bits set the debounce time before the PGOOD2 pin and flag are set. This debounce time
starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD2 is always
immediate (no debounce).
Bit 5
0
0
1
1
The following flags can also set the PGOOD2 pin: voltage continuity, OrFET disable, ACSNS, FLAGIN,
and OTP. This bit specifies whether these flags unconditionally set PGOOD2 or whether these flags
set PGOOD2 only if the flag action is not set to ignore (Bits[6:4] = 000) in the appropriate fault
configuration register (see Table 12 and Table 13).
0 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags always set the PGOOD2 pin.
1 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags set the PGOOD2 pin only if the
flag action is not set to “ignore. ”
This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = 0 V = on).
This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = 0 V = on).
This bit sets the polarity of the PSON input pin: 1 = inverted (low = 0 V = on).
Description
Enable this bit when operating in full-bridge mode. It affects the modulation high limit.
This value sets the minimum/maximum modulation limits relative to the nominal edge value. The
resolution depends on the switching frequency range.
Switching Frequency Range
48.8 kHz to 86.8 kHz
97.7 kHz to 183.8 kHz
195 kHz to 378.8 kHz
390.6 kHz to 625.0 kHz
Bit 6
0
1
0
1
Bit 4
0
1
0
1
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Typical Debounce Time (ms)
350
150
550
0
Typical Delay Time (ms)
350
150
550
0
Resolution Corresponding to LSB
160 ns
80 ns
40 ns
20 ns
Data Sheet