ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 60

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

ADP1046
VOLTAGE SENSE REGISTERS
Table 49. Register 0x31—VS3 Voltage Setting (Remote Voltage)
Bits
[7:0]
Table 50. Register 0x32—VS1 Overvoltage Limit (OVP)
Bits
[7:3]
2
[1:0]
Table 51. Register 0x33—VS2 and VS3 Overvoltage Limit (OVP)
Bits
[7:3]
2
Bit Name
VS2 and VS3
OVP setting
Regulating point
Bit Name
VS3 voltage setting
Bit Name
VS1 OVP setting
Reserved
OVP sampling
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register is used to set the output voltage (voltage differential at the VS3+ and VS3− pins). This
value is programmable from 0% to 150% of the nominal voltage. Each LSB corresponds to a 0.6%
increase. Setting this register to a value of 0xA0 gives an output voltage setting of 100% of the
nominal voltage. This is the default value that is stored in this register when the part is shipped from
the factory. Updating the VS3 voltage setting is a two-stage process. The user must first change the
value in this register; this information is stored in a shadow register. To latch the new VS3 voltage
setting into the state machine, the user must set the voltage reference GO bit (Register 0x7F[0]).
After that, the voltage changes with a limited slew rate (programmed in Register 0x5F[2:0]).
Description
Local overvoltage limit. This limit is programmable from 111.25% to 150% of the nominal VS1
voltage; 0x00 corresponds to 111.2%. Each LSB results in an increase of 1.25%. The VS1 OVP
threshold is calculated as follows:
VS1_OVP_Threshold = [(89 + VS1_OVP_Setting)/128] × 1.6 V
For example, if the VS1 OVP setting is 10, then
VS1_OVP_Threshold = [(89 + 10)/128] × 1.6 V = 1.2375 V
Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VS1 voltage.
Setting these bits to 7 gives an OVP limit of 120% of the nominal VS1 voltage.
Setting these bits to 15 gives an OVP limit of 130% of the nominal VS1 voltage.
Setting these bits to 31 gives an OVP limit of 150% of the nominal VS1 voltage.
Reserved.
The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP
threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using
these bits. If the number of samples is increased, the average voltage must be greater than the
OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average
voltage must be greater than the OVP threshold for both cycles.
Bit 1
0
0
1
1
Description
Local overvoltage limit. This limit is programmable from 111.25% to 150% of the nominal VSx
voltage; 0x00 corresponds to 111.2%. Each LSB results in an increase of 1.25%. The VSx OVP
threshold is calculated as follows:
VSx_OVP_Threshold = [(89 + VSx_OVP_Setting)/128] × 1.6 V
For example, if the VS2 OVP setting is 10, then
VS2_OVP_Threshold = [(89 + 10)/128] × 1.6 V = 1.2375 V
Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VSx voltage.
Setting these bits to 7 gives an OVP limit of 120% of the nominal VSx voltage.
Setting these bits to 15 gives an OVP limit of 130% of the nominal VSx voltage.
Setting these bits to 31 gives an OVP limit of 150% of the nominal VSx voltage.
When this bit is set, the
the
disabled.
ADP1046
uses the VS1 voltage as the regulating point during soft start and when the OrFET is
Bit 0
0
1
0
1
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ADP1046
Additional Sampling (μs)
0 (one sample sets the OVP flag)
80 (two samples set the OVP flag)
160 (three samples set the OVP flag)
240 (four samples set the OVP flag)
regulates from the VS3 node at all times. When this bit is not set,
Data Sheet