HIP6500BEVAL1 INTERSIL [Intersil Corporation], HIP6500BEVAL1 Datasheet - Page 11

• Manufacturer Part Number: HIP6500BEVAL1
• Description: Multiple Linear Power Controller with ACPI Control Interface
• Manufacturer: INTERSIL [Intersil Corporation]

voltage is done by means of an external resistor connected
between the FAULT/MSEL pin and ground. An internal 40 A
(typical) current source creates a voltage drop across this
resistor. Following every 3.3V
Soft-Start Circuit), this voltage is compared with an internal
reference and the setting is latched in. Based on this
comparison, the output voltage is set at either 2.5V
(R
that no capacitor is connected to the FAULT/MSEL pin; the
presence of a capacitive element at this pin can lead to false
memory voltage selection. See Figure 11 for details.
Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slew-
up speed of the output voltages controlled by the HIP6500B,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
I
C
V
capacitance and the voltage of an output (total charge
delivered to all outputs).
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the HIP6500B
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the HIP6500B
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
I
SS
COUT
SS
BG
SEL
C
- soft-start current (typically 10 A)
OUT
- soft-start capacitor
- bandgap voltage (typically 1.26V)
= 1k ), or 3.3V (R
=
x V
----------------------------- -
C
SS
OUT
I
SS
V
) - sum of the products between the
BG
C
SEL
OUT
11
SB
= 10k ). It is very important
V
ramp-up or chip reset (see
OUT
, where
HIP6500B
Layout Considerations
The typical application employing a HIP6500B is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible, but not excessively far from the clock chip or
the processor. Insure the VSEN2 connection is properly
sized to carry 250mA without significant resistive losses;
similar guideline applies to the VCLK output, which can
deliver as much as 800mA (typical). As the current for the
VCLK output is provided from the ATX 3.3V, the connection
from the 3V3 pin to the 3.3V plane should be sized to carry
the maximum clock output current while exhibiting negligible
voltage losses. Similarly, the current for the 3.3V
provided from the 5VSB pin, and the output current on pin
DRV2 from the 5V pin - for best results, insure these pins are
connected to their respective sources through adequate
traces. The pass transistors should be placed on pads
capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
C
C
C
V
HF4
BULK4
+12V
HF1
OUT1
+5V
Q3
V
C
FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
SB
OUT3
IN
HF3
Q2
C
BULK1
KEY
C
C
BULK3
VIA CONNECTION TO GROUND PLANE
SS
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
C
12V
3V3SB
SS
3V3DLSB
3V3DL
VCLK
12V
3V3
HIP6500B
GND
5VSB
5VDLSB
VSEN2
DRV2
5VDL
C
DLA
5VSB
5V
C
BULK5
Q1
C
IN
V
C
SB
OUT2
BULK2
V
Q5
OUT5
C
+5V
+3.3V
HF5
output is
C
IN
HF2
IN
Q4