HIP6500BEVAL1 INTERSIL [Intersil Corporation], HIP6500BEVAL1 Datasheet - Page 7

• Manufacturer Part Number: HIP6500BEVAL1
• Description: Multiple Linear Power Controller with ACPI Control Interface
• Manufacturer: INTERSIL [Intersil Corporation]

3V3SB (Pin 3)
This pin is the output of the internal 3.3V
(V
long as the 5VSB bias voltage is applied to the HIP6500B.
This pin is monitored for under-voltage events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(V
states (S0, S1) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6500B controls 5 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of two linear
controllers supplying the PCI slots’ 3.3V
and the 2.5V RDRAM or 3.3V SDRAM memory power
(V
3.3V
(V
voltage (V
functions necessary for complete ACPI implementation.
Initialization
The HIP6500B automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3V
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3V
status and the memory voltage (V
and the chip proceeds to ramp up the remainder of the
voltages, as required.
Operational Truth Tables
The EN3VDL and EN5VDL pins offer a choice of 4
configurations in terms of the overall system architecture
and supported features. Tables 1-3 describe the truth
combinations pertaining to each of the three outputs.
NOTE: Combination Not Allowed.
OUT1
OUT4
OUT2
OUT4
EN3V
SB
TABLE 1. 3.3V
0
0
0
0
1
1
1
1
). This internal regulator operates continuously for as
). This internal regulator operates only in active
), two linear regulators providing an always-present
), a dual switch controller supplying the 5V
(V
DL
OUT5
OUT1
), as well as all the control and monitoring
S5
), and a dedicated 2.5V clock chip supply
1
1
0
0
1
1
0
0
DUAL
SB
S3
1
0
1
0
1
0
1
0
finishes its ramp-up, the ENxVDL
OUTPUT (V
3V3
3.3V
3.3V
Note
3.3V
3.3V
3.3V
Note
7
0V
DL
MEM
OUT3
S0, S1 States (Active)
S3
Maintains Previous State
S4/S5
S0, S1 States (Active)
S3
Maintains Previous State
S4/S5
) setting are latched in
AUX
) TRUTH TABLE
SB
COMMENTS
regulator
power (V
DUAL
OUT3
SB
HIP6500B
)
As seen in Table 1, EN3VDL simply controls whether the
3.3VDUAL plane remains powered up during S4/S5 sleep
state.
NOTE: Combination Not Allowed.
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5V
sleep states.
NOTE: Combination Not Allowed.
As seen in Table 3, 2.5/3.3V
(suspend to RAM) sleep state only. The dual-voltage support
accommodates both SDRAM as well as RDRAM type
memories.
Not shown in any of the tables are the 3.3V
2.5V
the 5VSB ATX output is available. The 2.5V
operation is restricted by the chip’s POR and is only
available in active state (S0, S1). For additional information,
see the soft-start sequence diagrams.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S5) and vice versa.
R
10k
10k
10k
10k
1k
1k
1k
1k
EN5VDL
SEL
TABLE 3. 2.5/3.3V
CLK
TABLE 2. 5V
0
0
0
0
1
1
1
1
outputs. The 3.3V
S5
1
1
0
0
1
1
0
0
S5
1
1
0
0
1
1
0
0
S3
1
0
1
0
1
0
1
0
DUAL
MEM
S3
1
0
1
0
1
0
1
0
2.5/3.3V
OUTPUT (V
DUAL
OUTPUT (V
Note
Note
2.5V
2.5V
3.3V
3.3V
SB
0V
0V
MEM
5V
Note
Note
plane supports the S3-S5
5V
0V
0V
5V
5V
5V
MEM
output powers up as soon as
DL
output is maintained in S3
OUT5
OUT2
S0, S1 States (Active)
S3
Maintains Previous State
S4/S5
S0, S1 States (Active)
S3
Maintains Previous State
S4/S5
S0, S1 States (Active)
S3
Maintains Previous State
S5
S0, S1 States (Active)
S3
Maintains Previous State
S5
) TRUTH TABLE
) TRUTH TABLE
COMMENTS
COMMENTS
SB
CLK
and the
output