KS8893ML MICREL [Micrel Semiconductor], KS8893ML Datasheet - Page 64
![no-image](/images/no-image-200.jpg)
KS8893ML
Manufacturer Part Number
KS8893ML
Description
Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
1.KS8893ML.pdf
(106 pages)
- Current page: 64 of 106
- Download datasheet (650Kb)
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Bit
7
6
5
4
3
2
1
0
Note: Bits [2:0] are used for spanning tree support.
June 2005
Name
Ingress VLAN
Filtering
Discard non
PVID Packets
Force Flow
Control
Back Pressure
Enable
Transmit
Enable
Receive
Enable
Learning
Disable
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Do not change the default value.
= 1, the switch will discard packets whose VID
port membership in VLAN table bits [18:16] does
not include the ingress port.
= 0, no ingress VLAN filtering.
= 1, the switch will discard packets whose VID
does not match ingress port default VID.
= 0, no packets will be discarded
= 1, will always enable full duplex flow control on
the port, regardless of AN result.
= 0, full duplex flow control is enabled based on
AN result.
= 1, enable port’s half duplex back pressure
= 0, disable port’s half duplex back pressure
= 1, enable packet transmission on the port
= 0, disable packet transmission on the port
= 1, enable packet reception on the port
= 0, disable packet reception on the port
= 1, disable switch address learning capability
= 0, enable switch address learning
64
Default
0
0
0
Pin value during
reset:
For port 1,
P1FFC pin
For port 2,
P2FFC pin
For port 3, this
bit has no
meaning. Flow
control is set by
Reg. 6, bit 5.
0
1
1
0
M9999-063005
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