KS8893ML MICREL [Micrel Semiconductor], KS8893ML Datasheet - Page 8

• Manufacturer Part Number: KS8893ML
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
• Manufacturer: MICREL [Micrel Semiconductor]

Absolute Maximum Ratings
Operating Ratings
Electrical Characteristics
Timing Specifications...........................................................................................................................95
Reset Timing .......................................................................................................................................103
Reset Circuit........................................................................................................................................104
Selection of Isolation Transformers..................................................................................................105
Selection of Reference Crystal ..........................................................................................................105
Package Information...........................................................................................................................106
June 2005
EEPROM Timing ..................................................................................................................................................................95
SNI Timing............................................................................................................................................................................96
MII Timing.............................................................................................................................................................................97
RMII Timing ..........................................................................................................................................................................99
SPI Timing..........................................................................................................................................................................100
Auto-Negotiation Timing...................................................................................................................................................102
Register 111 (0x6F): TOS Priority Control Register 15..................................................................................................82
Register 112 (0x70): MAC Address Register 0 ..............................................................................................................82
Register 113 (0x71): MAC Address Register 1 ..............................................................................................................82
Register 114 (0x72): MAC Address Register 2 ..............................................................................................................82
Register 115 (0x73): MAC Address Register 3 ..............................................................................................................82
Register 116 (0x74): MAC Address Register 4 ..............................................................................................................82
Register 117 (0x75): MAC Address Register 5 ..............................................................................................................82
Register 118 (0x76): User Defined Register 1 ...............................................................................................................83
Register 119 (0x77): User Defined Register 2 ...............................................................................................................83
Register 120 (0x78): User Defined Register 3 ...............................................................................................................83
Register 121 (0x79): Indirect Access Control 0..............................................................................................................83
Register 122 (0x7A): Indirect Access Control 1 .............................................................................................................83
Register 123 (0x7B): Indirect Data Register 8 ...............................................................................................................83
Register 124 (0x7C): Indirect Data Register 7 ...............................................................................................................84
Register 125 (0x7D): Indirect Data Register 6 ...............................................................................................................84
Register 126 (0x7E): Indirect Data Register 5 ...............................................................................................................84
Register 127 (0x7F): Indirect Data Register 4................................................................................................................84
Register 128 (0x80): Indirect Data Register 3................................................................................................................84
Register 129 (0x81): Indirect Data Register 2................................................................................................................84
Register 130 (0x82): Indirect Data Register 1................................................................................................................84
Register 131 (0x83): Indirect Data Register 0................................................................................................................84
Register 132 (0x84): Digital Testing Status 0.................................................................................................................84
Register 133 (0x85): Digital Testing Control 0 ...............................................................................................................85
Register 134 (0x86): Analog Testing Control 0 ..............................................................................................................85
Register 135 (0x87): Analog Testing Control 1 ..............................................................................................................85
Register 136 (0x88): Analog Testing Control 2 ..............................................................................................................85
Register 137 (0x89): Analog Testing Control 3 ..............................................................................................................85
Register 138 (0x8A): Analog Testing Status ..................................................................................................................85
Register 139 (0x8B): Analog Testing Control 4..............................................................................................................85
Register 140 (0x8C): QM Debug 1 ................................................................................................................................85
Register 141 (0x8D): QM Debug 2 ................................................................................................................................85
Static MAC Address Table.............................................................................................................................................86
VLAN Table ...................................................................................................................................................................87
Dynamic MAC Address Table........................................................................................................................................88
MIB (Management Information Base) Counters.............................................................................................................89
Additional MIB Counter Information ...............................................................................................................................91
MAC Mode MII Timing ...................................................................................................................................................97
PHY Mode MII Timing....................................................................................................................................................98
Input Timing .................................................................................................................................................................100
Output Timing ..............................................................................................................................................................101
(1)
..............................................................................................................................92
(1)
..................................................................................................................93
(1)
..............................................................................................................92
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