AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 30
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AT90USB1286-16MU
Manufacturer Part Number
AT90USB1286-16MU
Description
Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT90USB1286-16MU.pdf
(434 pages)
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5.5.3
30
AT90USB64/128
Address Latch Requirements
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 5-6
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address, data and ALE ports, but the
RD and WR strobes will not toggle during internal access. When the External Memory Interface
is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM.
octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
7 through Tables 30-13 on pages 408 - 411. The D-to-Q propagation delay (t
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
wiring delay (dependent on the capacitive load).
Figure 5-5.
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
(this figure shows the wave forms without wait-states). When ALE goes from high-to-low,
External SRAM Connected to the AVR
h
Figure 5-5
= 5 ns. Refer to t
AVR
AD7:0
A15:8
ALE
WR
RD
illustrates how to connect an external SRAM to the AVR using an
PD
SU
).
) must not exceed address valid to ALE low (t
LAXX_LD
SU
).
TH
/t
LLAXX_ST
).
D
G
Q
in “External Data Memory Timing” Tables 30-
“I/O-Ports” on page
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
PD
AVLLC
) must be taken
73. The XMEM
7593A–AVR–02/06
) minus PCB
Fig-
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