AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 319
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AT90USB1286-16MU
Manufacturer Part Number
AT90USB1286-16MU
Description
Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT90USB1286-16MU.pdf
(434 pages)
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25.4
7593A–AVR–02/06
Prescaling and Conversion Timing
Figure 25-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
Figure 25-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. Alter-
natively, setting the ADHSM bit in ADCSRB allows an increased ADC clock frequency at the
expense of higher power consumption.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADEN
START
ADTS[2:0]
ADPS0
ADPS1
ADPS2
CK
DETECTOR
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
START
AT90USB64/128
CONVERSION
PRESCALER
LOGIC
CLK
ADC
319
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