AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 137
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AT91RM3400-AI-001
Manufacturer Part Number
AT91RM3400-AI-001
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91RM3400-AI-001.pdf
(461 pages)
- Current page: 137 of 461
- Download datasheet (6Mb)
Clock Switching Details
Master Clock Switching
Timings
Table 30. Clock Switching Timings (Worst Case)
1790A–ATARM–11/03
To
Main Clock
SLCK
PLLA Clock
PLLB Clock
From
PLLBCOUNT x SLCK +
PLLACOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLA Clock
2.5 x PLLB Clock
Main Clock
4.5 x SLCK
4 x SLCK +
4 x SLCK +
Table 30 gives the worst case timing required for the Master Clock to switch from one
selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the new
selected clock has to be added.
–
PLLACOUNT x SLCK
PLLBCOUNT x SLCK
2.5 x PLLA Clock +
2.5 x PLLB Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
5 x SLCK +
SLCK
–
PLLB COUNT x SLCK
2.5 x PLLA Clock +
3 x PLLA Clock +
3 x PLLA Clock +
3 x PLLB Clock +
1.5 x PLLB Clock
1 x Main Clock
PLLA Clock
4 x SLCK +
4 x SLCK +
4 x SLCK +
5 x SLCK
AT91RM3400
PLLACOUNT x SLCK
2.5 x PLLB Clock +
3 x PLLB Clock +
3 x PLLB Clock +
3 x PLLA Clock +
1.5 x PLLA Clock
1 x Main Clock
PLLB Clock
4 x SLCK +
4 x SLCK +
4 x SLCK +
5 x SLCK
137
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