AT32UC3B0512-A2UES ATMEL [ATMEL Corporation], AT32UC3B0512-A2UES Datasheet - Page 19
AT32UC3B0512-A2UES
Manufacturer Part Number
AT32UC3B0512-A2UES
Description
32-bit AVR Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT32UC3B0512-A2UES.pdf
(91 pages)
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Figure 6-1.
Overview of the AVR32UC CPU
Power/
OCD
Reset
system
control
AVR32UC CPU pipeline
MPU
Data memory controller
Instruction memory controller
High
High
CPU Local
Speed
High Speed Bus master
Speed
Bus
Bus
Bus slave
master
master
6.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 6-2 on page 20
shows an overview of the AVR32UC pipeline stages.
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