AT32UC3B0512-A2UES ATMEL [ATMEL Corporation], AT32UC3B0512-A2UES Datasheet - Page 61
AT32UC3B0512-A2UES
Manufacturer Part Number
AT32UC3B0512-A2UES
Description
32-bit AVR Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT32UC3B0512-A2UES.pdf
(91 pages)
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12.1.1.3
Power Manager
4. SPI Disable does not work in Slave mode
5. Module hangs when CSAAT=1 on CS0
6. Disabling SPI has no effect on flag TDRE flag
1. If the BOD level is higher than VDDCORE, the part is constantly under reset
2. When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
3. Clock sources will not be stopped in STATIC sleep mode if the difference between
4. Increased Power Consunption in VDDIO in sleep modes
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
SPI Disable does not work in Slave mode.
Fix/workaround
Read the last received data then perform a Software reset.
SPI data transfer hangs with CSAAT=1 in CSR0 and MODFDIS=0 in MR. When CSAAT=1
in CSR0 and mode fault detection is enabled (MODFDIS=0 in MR), the SPI module will not
start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MODFDIS in MR.
Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI
is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset
the TDRE flag by writing in the TDR. So if the SPI is disabled during a PDCA transfer, the
PDCA will continue to write data in the TDR (as TDRE stays high) until its buffer is empty,
and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, 2 NOP (minimum), disable SPI. When you want to continue the transfer:
Enable SPI, enable PDCA.
If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will
be in constant reset.
Fix/Workaround
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/workaround:
None.
CPU and PBx division factor is too big
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
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