ZLF645 MAXIM [Maxim Integrated Products], ZLF645 Datasheet - Page 77

• Manufacturer Part Number: ZLF645
• Description: Flash MCUs with Learning Amplification
• Manufacturer: MAXIM [Maxim Integrated Products]

Flash Controller Overview
19-4572; Rev 0; 4/09
Caution:
Executing Flash Memory Accesses Through the Flash Controller
Pages 0 through 2 (addresses
for Maxim
the ICP interface or by using the Flash Byte Programming interface.
The Flash Controller provides the appropriate Flash controls and timing for byte/word 
programming, Page Erase, Mass Erase, and reading of the Flash memory for Flash
accesses made by either the CPU or through the ICP interface. It also limits programming,
erase, and read access to the Flash memory based upon certain register and/or option bit
settings. External accesses through the ZLF645’s ICP or Flash Byte Programming Inter-
faces are limited by the Flash Controller based upon the programming of the ZLF645’s
Flash read/write protect bits in User Option Byte 1. Accesses by the CPU during code exe-
cution is limited based upon the programming of the Flash Controller’s Sector Protect
(FSEC) registers. All Flash memory accesses through the Flash Controller are prevented
unless the Flash Controller is in ‘unlocked’ state.
Flash Access Timing Control Programming Requirements
Before a program or erase operation can be executed by the Flash Controller on the Flash
memory, you must first configure the Flash Controller’s Flash frequency High and Low
Byte registers. These registers combine to form a 16-bit value (FFREQ) that is used by the
Flash Controller to control timing for Flash program and erase operations. For proper tim-
ing, the 16-bit binary Flash Frequency value must be programmed with the system clock
frequency (in kHz).
This 16-bit binary Flash Frequency value is calculated using the following equation:
Using a 16-bit value FFREQ value, the Flash Controller is able to provide correct program
and erase operation timing across a CPU clock frequency range of 1 MHz to 8 MHz.
The System Clock Frequency depends on the Flash memory programming of bit 2 of the
User Option Byte 1 and on the register programming of bit 0 of the SMR register and can
be equal to the clock input frequency on the XTAL1 pin, a divide by 2 of that input, a divide
by 16 of that input, or a divide by 32 of that input. Flash programming and erasure are not
supported for CPU clock frequencies below 1 MHz or above 8 MHz. The Flash Frequency
High and Low Byte registers must be loaded with the correct values.
FFREQ[15:0]
®
internal use and are inaccessible by you or programmer vendor, either through
=
System Clock Frequency (Hz)
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0000
1000
through
00BF
), of the Information Area are reserved
ZLF645 Series Flash MCUs
Product Specification
Flash Controller Overview
69