STM32F205XX_12 STMICROELECTRONICS [STMicroelectronics], STM32F205XX_12 Datasheet - Page 100

• Manufacturer Part Number: STM32F205XX_12
• Description: ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
5.3.17
Table 47.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
100/177
V
V
V
V
V
T
V
V
NF(NRST)
IH(NRST)
IH(NRST)
IL(NRST)
IL(NRST)
NRST_OUT
resistance must be minimum
Symbol
F(NRST)
hys(NRST)
R
PU
(1)
(1)
(1)
(1)
(1)
(1)
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
NRST pin characteristics
Figure 37. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
NRST input low level voltage
NRST input high level voltage
NRST input low level voltage
NRST input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
Generated reset pulse duration
Table
Table
47. Otherwise the reset is not taken into account by the device.
12.
External
reset circuit
PU
(~10% order)
(see
Parameter
(1)
Table
0.1 μF
.
NRST
44).
(2)
Doc ID 15818 Rev 9
(2)
V DD
Internal Reset source
R PU
2.7 V ≤ V
1.8 V ≤ V
CMOS ports
Conditions
V
TTL ports
V
DD
IN
> 2.7 V
=
DD
DD
V
DD
SS
≤ 3.6 V
≤ 3.6 V
supply voltage conditions summarized
Table 47
Filter
V
V
0.7V
SS
SS
Min
300
30
20
are derived from tests
IL(NRST)
2
-
-
−0.3
−0.3
STM32Fxxx
DD
Internal Reset
max level specified in
Typ
200
40
-
-
-
-
-
-
-
to the series
V
V
0.3V
STM32F20xxx
DD
DD
Max
100
0.8
50
-
-
-
+0.3
+0.3
DD
ai14132c
Unit
mV
kΩ
ns
ns
µs
V
V