MC908QL4 FREESCALE [Freescale Semiconductor, Inc], MC908QL4 Datasheet - Page 183

• Manufacturer Part Number: MC908QL4
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

15.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
Freescale Semiconductor
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When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TSCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Writing a 1 to CHxF has no effect.
This read/write bit enables TIM interrupt service requests on channel x.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0.
Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to
general-purpose I/O.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x interrupt requests enabled
0 = Channel x interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Reset:
Reset:
Read:
Write:
Read:
Write:
Figure 15-10. TIM Channel 1 Status and Control Register (TSC1)
Figure 15-9. TIM Channel 0 Status and Control Register (TSC0)
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
= Unimplemented
CH0IE
CH1IE
6
0
6
0
MC68HC908QL4 Data Sheet, Rev. 7
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0
Registers
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