MC9S12DJ256 MOTOROLA [Motorola, Inc], MC9S12DJ256 Datasheet - Page 113

• Manufacturer Part Number: MC9S12DJ256
• Description: MC9S12DT256 Device User Guide V03.03
• Manufacturer: MOTOROLA [Motorola, Inc]

A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
The grey boxes show the calculation for f
for f
The VCO Gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
OSC
= 4MHz and a 25MHz bus clock.
1
, f
1
and i
f
osc
K
V
ch
from Table A-16.
=
K
K
refdv+1
Figure A-2 Basic PLL functional diagram
1
=
1
e
–
---------------------- -
f
K
i
1
ch
1
f
–
ref
VDDPLL
f
1V
VCO
vco
K
=
V
= 50MHz and f
–
100
f
cmp
C
C
p
Loop Divider
s
e
Detector
= 316.7Hz/
----------------------- -
Phase
60 50
synr+1
–
K
100
ref
1
–
MC9S12DT256 Device User Guide — V03.03
R
= 1MHz. E.g., these frequencies are used
= -90.48MHz/V
XFC Pin
1
2
VCO
K
V
f
vco
111