MC9S12E128 MOTOROLA [Motorola, Inc], MC9S12E128 Datasheet - Page 79

• Manufacturer Part Number: MC9S12E128
• Description: MC9S12E-Family Device User Guide V01.04
• Manufacturer: MOTOROLA [Motorola, Inc]

Function 1
NOTES:
Pin Name
1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For example,
PU[7:6]
PU[5:4]
PQ[6:4]
PQ[3:0]
PU[3:0]
PT[7:4]
PT[3:0]
in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to the S12
MEBI Block Guide for PEAR register details.
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
NOTE:
NOTE:
Function 2
Pin Name
FAULT[3:0]
IOC1[7:4]
IOC0[7:4]
PW1[5:4]
IOC2[7:4]
Signals shown in bold are not available in the 80 pin package.
If the port pins are not bonded out in the chosen package the user should initialize the
registers to be inputs with enabled pull resistance to avoid excess current consumption.
This applies to the following pins:
(80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4]
IS[6:4]
RXD1
RXD0
MOSI
MISO
TXD1
TXD0
SCK
SS
—
Function 3
Pin Name
PW1[3:0]
Freescale Semiconductor, Inc.
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For More Information On This Product,
Domain
Power
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
Go to: www.freescale.com
PERQ/
PERQ/
PERU/
PERU/
PERU/
CTRL
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERT/
PERT/
PPSQ
PPSQ
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPST
PPST
PPSU
PPSU
PPSU
Internal Pull
Resistor
Reset State
Device User Guide — 9S12E128DGV1/D V01.04
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Up
Up
Up
Up
Up
Up
Up
Up
Port Q I/O Pins, IS[6:4] input
Port Q I/O Pins, Fault[3:0] input
Port S I/O Pin, SPI SS signal
Port S I/O Pin, SPI SCK signal
Port S I/O Pin, SPI MOSI signal
Port S I/O Pin, SPI MISO signal
Port S I/O Pin, SCI1 transmit signal
Port S I/O Pin, SCI1 receive signal
Port S I/O Pin, SCI0 transmit signal
Port S I/O Pin, SCI0 receive signal
Port T I/O Pins, timer (TIM1)
Port T I/O Pins, timer (TIM0)
Port U I/O Pins
Port U I/O Pins, PWM outputs
Port U I/O Pins, timer (TIM2), PWM outputs
Description
79