M306V0ME-107FP MITSUBISHI [Mitsubishi Electric Semiconductor], M306V0ME-107FP Datasheet - Page 126

• Manufacturer Part Number: M306V0ME-107FP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

126
Figure 2.11.27 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
RxD
Signal conductor level
(Note 1)
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
RxD
TxD
Signal conductor level
(Note 1)
Receive complete
flag (RI)
Receive interrupt
request bit (IR)
2
2
2
2
Note: Equal in waveform because TxD
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Start
ST
ST
ST
Start
ST
bit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
bit
D
D
D
D
Data is set in UARTi transmit buffer register
0
0
0
0
D
D
D
D
1
1
1
1
Tc
Tc
D
D
D
D
2
2
2
2
D
D
2
D
D
3
3
3
and RxD
3
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
2
D
D
are connected.
Transferred from UARTi transmit buffer register to UARTi transmit register
D
D
6
6
6
6
D
D
D
Parity
D
Parity
7
7
7
7
bit
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
P
P
P
P
Cleared to “0” when interrupt request is accepted, or cleared by software
SP
SP
SP
SP
fi : frequency of BRGi count source (f
f
n : value set to BRGi
fi : frequency of BRGi count source (f
f
n : value set to BRGi
EXT
EXT
Stop
Stop
bit
bit
Read to receive buffer
: frequency of BRGi count source (external clock)
: frequency of BRGi count source (external clock)
ST
ST
The level is detected by the
interrupt routine.
ST
ST
A “L” level returns from TxD
the occurrence of a parity error.
A “L” level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
D
D
D
D
1
1
1
and ON-SCREEN DISPLAY CONTROLLER
1
D
D
D
D
2
2
2
2
EXT
EXT
D
D
D
MITSUBISHI MICROCOMPUTERS
D
3
3
3
3
D
D
D
D
4
4
4
4
M306V0ME-XXXFP
1
D
1
D
D
D
, f
, f
5
5
2
5
5
8
8
2
due to
, f
D
D
, f
D
due to
D
6
6
32
32
6
6
)
D
D
)
D
D
7
7
7
7
P
P
P
P
M306V0EEFP
Read to receive buffer
SP
SP
SP
SP
The level is
detected by the
interrupt routine.
Rev. 1.0