MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 442

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Queued Analog-to-Digital Converter (QADC)
19.8.5 Control Registers
19.8.5.1 QADC Control Register 0 (QACR0)
Advance Information
442
Address: 0x00ca_000a and 0x00ca_000b
Reset:
Reset:
Read:
Read:
Write:
Write:
This subsection describes the QADC control registers.
QADC Control Register 0 (QACR0) establishes the QADC sampling
clock (QCLK) with prescaler parameter fields and defines whether
external multiplexing is enabled. Typically, these bits are written once
when the QADC is initialized and not changed thereafter.
Read: Anytime
Write: Anytime except during stop mode
MUX — Externally Multiplexed Mode Bit
The MUX bit configures the QADC for operation in externally
multiplexed mode, which affects the interpretation of the channel
numbers and forces the MA[1:0] pins to be outputs.
Freescale Semiconductor, Inc.
Figure 19-8. QADC Control Register 0 (QACR0)
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Externally multiplexed, up to 18 possible channels
0 = Internally multiplexed, up to 8 possible channels
Bit 15
MUX
Bit 7
0
0
0
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
QPR6
14
0
0
6
0
QPR5
13
0
0
5
0
QPR4
TRG
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
0
4
1
QPR3
11
0
0
3
0
QPR2
10
0
0
2
0
QPR1
9
0
0
1
1
MOTOROLA
QPR0
Bit 8
Bit 0
0
0
1