S9S08AW16A FREESCALE [Freescale Semiconductor, Inc], S9S08AW16A Datasheet - Page 73

• Manufacturer Part Number: S9S08AW16A
• Description: HCS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.9.3
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
Freescale Semiconductor
Reset
BDFR
Field
Field
ILAD
LVD
ICG
3
2
1
0
W
R
1
BDFR is writable only through serial background debug commands, not from user programs.
System Background Debug Force Reset Register (SBDFR)
Illegal Address — Reset was caused by an attempt to access a designated illegal address.
0 Reset not caused by an illegal address access.
1 Reset caused by an illegal address access.
Illegal address areas in the MC9S08AC16 are:
0x0470 - 0x17FF
0x1860 - 0xBFFF — Gap from end of high page registers to start of Flash memory
Unused and reserved locations in register areas are not considered illegal addresses and do not trigger illegal
address resets.
Internal Clock Generation Module Reset — Reset was caused by an ICG module reset.
0 Reset not caused by ICG module.
1 Reset caused by ICG module.
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage,
an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This
bit cannot be written from a user program.
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
— Gap from end of RAM to start of high page registers
Table 5-4. SRS Register Field Descriptions (continued)
0
0
6
Table 5-5. SBDFR Register Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
0
0
4
Description
Description
Chapter 5 Resets, Interrupts, and System Configuration
3
0
0
0
0
2
0
0
1
BDFR
0
0
0
1
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