SAH-C515 SIEMENS [Siemens Semiconductor Group], SAH-C515 Datasheet - Page 109
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SAH-C515
Manufacturer Part Number
SAH-C515
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.SAH-C515.pdf
(160 pages)
- Current page: 109 of 160
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6.4.3 A/D Conversion Timing
An A/D conversion is internally started by writing the SFR DAPR. A write to SFR DAPR will start a
new conversion even if a conversion is currently in progress. The conversion begins with the next
machine cycle, and the BSY flag in SFR ADCON will be set.
The A/D conversion procedure is divided into three parts :
Sample Time
During this time the internal capacitor array is connected to the selected analog input channel and
is loaded with the analog voltage to be converted. The analog voltage is internally fed to a voltage
comparator. With beginning of the sample phase the BSY bit in SFR ADCON is set.
Conversion Time t
During the conversion time the analog voltage is converted into a 8-bit digital value using the
successive approximation technique with a binary weighted capacitor network.
Write Result Time t
At the result phase the conversion result is written into the ADDAT register.
The total A/D conversion time is defined by t
t
This figure also shows how an A/D conversion is embedded into the microcontroller cycle scheme
using the relation 6 x t
and the interrupt flag (IADC) during an A/D conversion.
Semiconductor Group
CO
– Sample phase (t
– Conversion phase (t
– Write result phase (t
. The duration of the three phases of an A/D conversion is specified as shown in figure 6-33.
t S
:
CO
WR
S
IN
:
), used for sampling the analog input voltage.
:
= 1 instruction cycle. It also shows the behaviour of the busy flag (BSY)
CO
WR
), used for the real A/D conversion.
), used for writing the conversion result into the ADDAT register.
ADCC
6-66
which is the sum of the two phase times t
On-Chip Peripheral Components
C515
S
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