SAH-C515 SIEMENS [Siemens Semiconductor Group], SAH-C515 Datasheet - Page 61
SAH-C515
Manufacturer Part Number
SAH-C515
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.SAH-C515.pdf
(160 pages)
- Current page: 61 of 160
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6.2.1.2
Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-
32 prescaler. Figure 6-9 shows the mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s
to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an
interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1
(setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width
measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD.
The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0
are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for
the corresponding timer 1 signals in figure 6-9. There are two different gate bits, one for timer 1
(TMOD.7) and one for timer 0 (TMOD.3).
Figure 6-9
Timer/Counter 0, Mode 0: 13-Bit Timer/Counter
Semiconductor Group
Gate
P3.2/INTO
P3.4/T0
Mode 0
OSC
=1
÷ 12
<
_
1
TR0
C/T = 0
C/T = 1
&
6-18
Control
On-Chip Peripheral Components
(5
TL0
Bits)
(8
TH0
Bits)
TF0
Interrupt
MCS02583
C515
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