STM1404ARMBQ6F STMICROELECTRONICS [STMicroelectronics], STM1404ARMBQ6F Datasheet
STM1404ARMBQ6F
Related parts for STM1404ARMBQ6F
STM1404ARMBQ6F Summary of contents
Page 1
Features ■ STM1404 supports FIPS-140 security level 4 – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm (SAL) on tamper detection – Over/under operating temperature detector – Over/under temperature thresholds are customer-selectable and factory- programmed ...
Page 2
Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
STM1404 4.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
STM1404 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Description 1 Description The STM1404 family of security supervisors are a low power family of intrusion (tamper) detection chips targeted at manufacturers of POS terminals and other systems, to enable them to meet physical and/or environmental intrusion monitoring requirements as ...
Page 7
STM1404 Figure 1. Logic diagram 1. V only for STM1404A; V REF 2. Normal mode: low when V battery. 3. SAL, RST, PFO, and BLD are open drain. Table 2. Signal names (1) Vccsw MR PFI ...
Page 8
Description Figure 2. QFN16 connections Note: See Section 2: Pin descriptions on page 11 1. Normal mode: low when V battery. 2. SAL, RST, PFO, and BLD are open drain only for STM1404A; V REF Figure 3. Block ...
Page 9
STM1404 Figure 4. Hardware hookup Unregulated Voltage 1. Normal mode: low when V battery. 2. Capacitor (C) is typically ≥ 10 µF. 3. Open drain 4. Diode is required for battery reverse charge protection only for STM1404A; V ...
Page 10
Description Figure 6. Tamper pin (TP open typical is 10 MΩ. Resistors must be protected against conductive materials. Figure 7. Tamper pin (TP closed typical is 10 MΩ. Resistors must be protected against conductive materials. Figure ...
Page 11
STM1404 2 Pin descriptions See Figure 1: Logic diagram connected to this device. 2.1 SAL, security alarm output (open drain) This signal can be generated when ANY of the following conditions occur: ● V > where V INT ...
Page 12
Pin descriptions If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows: 1. STM1404A (V operate in normal mode; 2. STM1404B (V high when this occurs; and 3. STM1404C (V high ...
Page 13
STM1404 2 reference voltage output (1.237, typ) REF This is valid only when pulled to ground with an internal 100 kΩ resistor. This is an optional feature REF available on the STM1404A. On the STM1404B/C, ...
Page 14
Operation 3 Operation 3.1 Reset input The STM1404 security supervisor asserts a reset signal to the MCU whenever V below the reset threshold (V RST is guaranteed logic low for 0 V < backup battery, ...
Page 15
STM1404 Table 3. I/O status in battery backup Pin V Connected to V OUT V Disconnected from V CC PFI Disabled PFO Logic low MR Disabled RST Logic low V Connected to V BAT Vccsw Logic high V Pulled to ...
Page 16
Operation Figure 9. Power-fail comparator waveform RST V SW (2.4V) PFO RST 3.5 Negative-going V The STM1404 devices are relatively immune to negative-going V Figure 23 on page 22 + 0.3 V and ending below the reset ...
Page 17
STM1404 4 Tamper detection 4.1 Physical There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high (NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see Table 7 ...
Page 18
Typical operating characteristics 5 Typical operating characteristics Note: Typical values are at T Figure 11. V BAT 220 200 180 160 140 120 100 –60 Figure 12. Supply current vs. temperature (no load ...
Page 19
STM1404 Figure 13. V PFI 1.255 1.250 1.245 1.240 1.235 1.230 1.225 Figure 14. Reset comparator propagation delay vs. temperature –60 Figure 15. Power-up t 215 24 22 210 20 18 205 ...
Page 20
Typical operating characteristics Figure 17. PFI to PFO propagation delay vs. temperature –60 Figure 18. RST output voltage vs. supply voltage 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 Figure ...
Page 21
STM1404 Figure 20. Power-fail comparator response time (assertion) 4.0 3.0 2.0 1.0 0.0 Figure 21. Power-fail comparator response time (de-assertion) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 PFO PFI 2µs/div PFO PFI 2 µs/div Typical operating characteristics 1.45 ...
Page 22
Typical operating characteristics Figure 22 –60 Figure 23. Maximum transient duration vs. reset threshold overdrive 250 200 150 100 50 22/36 to reset propagation delay vs. temperature –40 – ...
Page 23
STM1404 6 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
Page 24
DC and AC parameters 7 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests ...
Page 25
STM1404 Figure 26. STM1404 switchover diagram, condition 3. 2.4V Figure 27. STM1404 switchover diagram, condition 3. 2.4V Table 6. DC and AC characteristics Alter- ...
Page 26
DC and AC parameters Table 6. DC and AC characteristics (continued) Alter- Sym Description native Internal switched V supply voltage (battery TPU2 backup) Input leakage current (MR) Input leakage current I LI (PFI) Input leakage current (TP1-TP4) I Output leakage ...
Page 27
STM1404 Table 6. DC and AC characteristics (continued) Alter- Sym Description native V battery backup OH V OHB (Vccsw) Pull-up supply voltage (open drain) Power-fail comparator V PFI input threshold PFI PFI hysteresis PFI to PFO t PFD propagation delay ...
Page 28
DC and AC parameters Table 6. DC and AC characteristics (continued) Alter- Sym Description native Reset thresholds (9) V Reset threshold RST t RST pulse width rec Push-button reset input pulse width MLMH RST ...
Page 29
STM1404 Table 7. Physical and environmental tamper detection levels Sym Parameter V Overvoltage trip level HV V Undervoltage trip level LV SAL propagation delay time (after over/under voltage detection) Trip point for NH physical tamper V HTP input pins (TP ...
Page 30
Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and ...
Page 31
STM1404 Table 8. QFN16 – 16-lead, quad, flat package, no lead body size mechanical data Symb ddd Ch N Figure 30. QFN16 – 16-lead, quad, ...
Page 32
Part numbering 9 Part numbering Table 9. Ordering information scheme (see Example: Device type STM1404: over/under temperature detect V status (SAL = active-low) OUT ON; Vccsw = normal mode OUT ( High-Z; Vccsw ...
Page 33
STM1404 Figure 31. Topside marking information 1. Options codes (for V OUT (for reset threshold (for battery low voltage detect threshold) X ...
Page 34
Revision history 10 Revision history Table 10. Document revision history Date Revision 11-Oct-2004 26-Nov-2004 22-Dec-2004 03-Feb-2005 25-Feb-2005 06-May-2005 05-Aug-2005 06-Jan-2006 08-Feb-2007 21-Aug-2008 34/36 1 First edition Corrected footprint dimensions; update characteristics (Figure 1 ...
Page 35
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...