M40SZ100WMH STMICROELECTRONICS [STMicroelectronics], M40SZ100WMH Datasheet - Page 8

• Manufacturer Part Number: M40SZ100WMH
• Description: 5V or 3V NVRAM SUPERVISOR FOR LPSRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M40SZ100Y, M40SZ100W
OPERATION
The M40SZ100Y/W, as shown in Figure 7, page 5,
can control one (two, if placed in parallel) standard
low-power SRAM. This SRAM must be configured
to have the chip enable input disable all other input
signals. Most slow, low-power SRAMs are config-
ured like this, however many fast SRAMs are not.
During normal operating conditions, the condi-
tioned chip enable (E
chip enable (E) input pin with timing shown in Ta-
ble 6, page 10. An internal switch connects V
V
0.3V (I
When V
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
as V
(V
tection value associated with V
ble 5, page 7.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
E
ing the SRAM. A power failure during a WRITE cy-
cle may corrupt data at the currently addressed
location, but does not jeopardize the rest of the
SRAM's contents. At voltages below V
the user can be assured the memory will be write
protected within the Write Protect Time (t
vided the V
ble 6, page 10).
As V
disconnects V
to V
(V
age V
I
When V
back to the supply voltage. Output E
active for t
8/19
OUT2
OUT
CON
PFD
SO
OUT
CC
). Below the V
CC
. This switch has a voltage drop of less than
). For the M40SZ100Y/W the power fail de-
(see Table 5, page 7).
is unconditionally driven high, write protect-
OHB
OUT1
CC
. This occurs at the switchover voltage
falls below an out-of-tolerance threshold
continues to degrade, the internal switch
CC
CER
CC
to the SRAM and can supply current
degrades during a power failure, E
).
rises above V
CC
fall time does not exceed t
(120ms maximum) after the power
and connects the internal battery
SO
, the battery provides a volt-
CON
) output pin follows the
SO
, V
PFD
OUT
is shown in Ta-
CON
is switched
PFD
F
is held in-
WPT
(see Ta-
(min),
) pro-
CC
WPT
CON
to
,
supply has reached V
put, to allow for processor stabilization (see Figure
11, page 10).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40SZ100Y/W NVRAM Control-
ler. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40SZ100Y/W and SRAMs to be “Don't care”
once V
page 9). The SRAM should also guarantee data
retention down to V
cess time must be sufficient to meet the system
needs with the chip enable propagation delays in-
cluded.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
SRAMs can then be added to the I
the M40SZ100Y/W to determine the total current
requirements for data retention. The available bat-
tery capacity for the SNAPHAT
(see Table 13, page 17) can then be divided by
this current to determine the amount of data reten-
tion available.
CAUTION: Take care to avoid inadvertent dis-
charge through V
been attached.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
CC
falls below V
OUT
CC
PFD
and E
= 2.0V. The chip enable ac-
PFD
, independent of the E in-
(min) (see Figure 10,
CON
®
after battery has
of your choice
CCDR
value of