X4163 INTERSIL [Intersil Corporation], X4163 Datasheet - Page 15
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X4163
Manufacturer Part Number
X4163
Description
CPU Supervisor with 16K EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
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CAPACITANCE (T
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Notes: (1) Typical values are for T
Symbol
Symbol
C
t
t
t
t
t
t
t
HD:DAT
SU:STO
SU:STA
HD:STA
SU:DAT
C
SU:WP
HD:WP
t
t
OUT
f
t
HIGH
LOW
t
BUF
t
SCL
Cb
t
IN
DH
t
AA
t
(2) Cb = total capacitance of one bus line in pF.
IN
R
F
(4)
(4)
RESET
SDA
or
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
Output Capacitance (SDA, RST/RST)
Input Capacitance (SCL, WP)
A
= 25° C, f = 1.0 MHz, V
5V
15
1533:
100pF
A
= 25° C and V
For V
and I
Parameter
OL
OL
= 0.4V
= 3 mA
CC
Parameter
= 5.0V
CC
= 5V)
X4163, X4165
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
Max.
8
6
Unit
20 + .1Cb
20 + .1Cb
pF
pF
Min.
100
0.1
1.3
1.3
0.6
0.6
0.6
0.6
0.6
50
50
0
0
0
0.1V
10ns
0.5V
Standard output load
Test Conditions
Max.
CC
CC
400
300
300
400
0.9
V
V
OUT
to 0.9V
IN
= 0V
= 0V
April 13, 2005
CC
Unit
kHz
pF
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
FN8120.0