X4283 INTERSIL [Intersil Corporation], X4283 Datasheet - Page 12

• Manufacturer Part Number: X4283
• Description: CPU Supervisor with 128K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge,
Figure 14. Sequential Read Sequence
X4283/85 Addressing
S
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
– one bits of ‘0’.
– next two bits are the device address select bits S1
– one bit of the slave command byte is a R/W bit. The
LAVE
array
and S0.
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
Signals from
Signals from
A
the Slave
the Master
SDA Bus
DDRESS
B
YTE
12
Address
Slave
1
A
C
K
Data
(1)
X4283, X4285
A
C
K
Data
(2)
indicating it requires additional data. The device con-
tinues to output data for each acknowledge received.
The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
0000
acknowledge received. Refer to Figure 14 for the
acknowledge and data transfer sequence.
– After loading the entire Slave Address Byte from the
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
H
and the device continues to output data for each
C
A
K
(n is any integer greater than 1)
Data
(n-1)
A
C
K
Data
(n)
March 29, 2005
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FN8121.0