XR16L78464-TQFP EXAR [Exar Corporation], XR16L78464-TQFP Datasheet - Page 12

• Manufacturer Part Number: XR16L78464-TQFP
• Description: HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
• Manufacturer: EXAR [Exar Corporation]

XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
The THR and RHR register addresses for channel 0 to channel 7 is shown in
for channels 0 to 3 are located at address 0x00, 0x10, 0x20 and 0x30 respectively. Transmit data byte is loaded
to the THR when writing to that address and receive data is unloaded from the RHR register when reading that
address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only
write or read in bytes.
Automatic RTS/DTR flow control is used to prevent data overrun to the local receiver FIFO. The RTS#/DTR#
output pin is used to request remote unit to suspend/resume data transmission. The flow control features are
individually selected to fit specific application requirement (see
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (HIGH) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level for Trigger Tables A-C
unloaded to the next trigger level below the programmed trigger level.
For Trigger Table D (or programmable trigger levels), the RTS# output pin is de-asserted when the the RX
FIFO level reaches the RX trigger level plus the hysteresis level and is asserted when the RX FIFO level falls
below the RX trigger level minus the hysteresis level.
However, even under these conditions, the 788 will continue to accept data until the receive FIFO is full if the
remote UART transmitter continues to send data.
2.9
2.10
Select RTS (and CTS) or DTR (and DSR) through MCR bit-2.
Enable auto RTS/DTR flow control using EFR bit-6.
The auto RTS or auto DTR function must be started by asserting the RTS# or DTR# output pin (MCR bit-1 or
bit-0 to a logic 1, respectively) after it is enabled.
If using programmable RX FIFO trigger levels, hysteresis levels can be selected via FCTR bits 3-0.
If used, enable RTS/DTR interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR bit-5 will be set to 1.
THR and RHR Register Locations
Automatic RTS/DTR Hardware Flow Control Operation
C H 0 0x00 R ead R H R
C H 0 0x00 W rite T H R
C H 1 0x10 W rite T H R
C H 2 0x20 W rite T H R
C H 3 0x30 W rite T H R
C H 1 0x10 R ead R H R
C H 2 0x20 R ead R H R
C H 3 0x30 R ead R H R
T
ABLE
TH R and RH R Address Locations For CH 0 to CH 3 (16C 550 Com patible)
5: T
(See Table
RANSMIT AND
14). The RTS# output pin will be asserted (LOW) again after the FIFO is
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
R
ECEIVE
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
D
12
ATA
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
R
EGISTER
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
Figure
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
, 16C550
10):
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
Table 5
COMPATIBLE
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
784TH R R H R 1
below. The THR and RHR
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
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áç
áç
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REV. 1.2.0