XR16L78464-TQFP EXAR [Exar Corporation], XR16L78464-TQFP Datasheet - Page 21

• Manufacturer Part Number: XR16L78464-TQFP
• Description: HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
• Manufacturer: EXAR [Exar Corporation]

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REV. 1.2.0
The XR16L784 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. Register INT3 is not used in the 784 UART, only in the 8-channel XR16L788. The 3 registers
are in the device configuration register address space.
All 4 registers default to logic zero (as indicated in square braces) for no interrupt pending. All 4 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1 and INT2 show the details of the source of each channel’s interrupt with its unique 3-bit
encoding.
interrupts are masked in the device configuration registers,
enabed) by the 784 when awakened from sleep if all 4 channels were placed in the sleep mode previously.
Each bit in the INT0 register gives an indication of the channel that has requested service.
For example, bit-0 represents channel 0 and bit-3 indicates channel 3. Bits 4 to 7 are reserved and remains at
logic zero. Logic one indicates the channel N [3:0] has called for service. The interrupt bit clears after reading
the appropiate register of the interrupting UART channel register (ISR, LSR and MSR).
interrupt clearing details.
INT2 and INT1 provide a 12-bit (3 bits per channel) encoded interrupt indicator.
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt .
For other channels, interrupt 7 is reserved.
.
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F
3.1.1
3.1.1.1
3.1.1.2
IGURE
Bit
2
Reserved
14. T
Bit
1
Figure 14
The Global Interrupt Source Registers
Bit
0
HE
INT0 Channel Interrupt Indicator:
INT1 and INT2 Interrupt Source Locator
INT3 Register
Bit
G
2
Reserved
LOBAL
shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep wake-up
Bit
1
Bit
0
I
NTERRUPT
Bit
2
INT3 (Rsvd)
Reserved
R svd
B it-7
[0x00]
Bit
1
R
Bit
R svd
0
B it-6
In d ivid u a l U A R T C h a n n e l In te rru p t S ta tu s
EGISTERS
Bit
2
Reserved
R svd
B it-5
INT0, INT1, INT2 and INT3
Bit
[0x00]
1
INT2
, INT0, INT1, INT2
Interrupt Registers,
INT2 Register
IN T0 Register
Bit
R svd
B it-4
0
Bit
21
2
Channel-3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
C h -3
B it-3
Bit
1
[0x00]
TIMERCNTL and SLEEP .
INT1
B it-2
C h -2
Bit
0
Bit
AND
2
Channel-2
C h -1
B it-1
Rsvd
Bit-7
Bit
1
INT3
[0x00]
INT0
Rsvd
Bit-6
C h -0
B it-0
Bit
0
Rsvd
Bit-5
Bit
2
Channel-1
INT0 Register
Rsvd
Bit-4
An interrupt is generated (if
INT1 Register
Bit
1
Table 9
Ch-3
Bit-3
Bit
0
Ch-2 Ch-1 Ch-0
Bit-2
Bit
2
Channel-0
See Table 13
shows the 3 bit
Bit-1
Bit
1
XR16L784
Bit-0
Bit
0
for